AD9915(RevA) Просмотр технического описания (PDF) - Analog Devices
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AD9915 Datasheet PDF : 48 Pages
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AD9915
Parameter
Min
PARALLEL PORT TIMING
Write Timing
Address Setup Time to WR Active 1
Address Hold Time to WR Inactive
Data Setup Time to WR Inactive
3.8
Data Hold Time to WR Inactive
WR Minimum Low Time
WR Minimum High Time
Minimum WR Time
Read Timing
Address to Data Valid
Address Hold to RD Inactive
RD Active to Data Valid
RD Inactive to Data Tristate
RD Minimum Low Time
RD Minimum High Time
SERIAL PORT TIMING
SCLK Clock Rate (1/tCLK )
SCLK Pulse Width High, tHIGH
1.5
SCLK Pulse Width Low, tLOW
5.1
SDIO to SCLK Setup Time, tDS
4.9
SDIO to SCLK Hold Time, tDH
SCLK Falling Edge to Valid Data on
SDIO/SDO, tDV
CS to SCLK Setup Time, tS
4
CS to SCLK Hold Time, tH
CS Minimum Pulse Width High, tPWH
4
DATA PORT TIMING
D[31:0] Setup Time to SYNC_CLK
2
D[31:0] Hold Time to SYNC_CLK
F[3:0] Setup Time to SYNC_CLK
2
F[3:0] Hold Time to SYNC_CLK
IO_UPDATE Pin Setup Time to
2
SYNC_CLK
IO_UPDATE Pin Hold Time to
SYNC_CLK
Profile Pin Setup Time to SYNC_CLK
Profile Pin Hold Time to SYNC_CLK
2
DR_CTL/DR_HOLD Setup Time to
2
SYNC_CLK
DR_CTL/DR_HOLD Hold Time to
SYNC_CLK
DATA LATENCY (PIPELINE DELAY)
Single Tone Mode (Matched Latency
Disabled)
Frequency
Phase
Amplitude
Single Tone Mode (Matched Latency
Enabled)
Frequency
Phase
Amplitude
Typ Max
0
0
2.1
3.8
10.5
92
0
69
50
69
50
80
0
78
0
0
0
0
0
0
320
296
104
320
320
320
Data Sheet
Unit
Test Conditions/Comments
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
SCLK duty cycle = 50%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles = fS = system clock frequency
in GHz
SYSCLK cycles
SYSCLK cycles
Rev. A | Page 6 of 48
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