AD9898 Просмотр технического описания (PDF) - Analog Devices

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AD9898

CCD Signal Processor with Precision Timing™ Generator

Analog Devices 

AD9898

H-Driver and RG Outputs

In addition to the programmable timing positions, the AD9898

features on-chip output drivers for the RG and H1–H2 outputs.

They are sufficiently powerful to directly drive the CCD inputs.

The H-driver current can be adjusted for optimum rise/fall time

into a particular load by using the H1DRV and H2DRV regis-

ters (Addr 0x04). The RG drive current is adjustable using the

RGDRV register (Addr 0x04). The H1DRV and H2DRV regis-

ter is adjustable in 4.3 mA increments. The RGDRV register is

adjustable in 2.15 mA increments. All DRV registers have a setting

of 0 equal to OFF or three-state, and the maximum setting of 7.

As shown in Figure 13, the H2 output is the inverse of H1. The

internal propagation delay resulting from the signal inversion is

less than 1 ns, which is significantly less than the typical rise

time driving the CCD load. This results in an H1/H2 crossover

voltage of approximately 50% of the output swing. The cross-

over voltage is not programmable.

Digital Data Outputs

The AD9898 DOUT[9:0] and DCLK phases are independently

programmable using the DOUTPHASE register (Addr 0x02)

and DCLKPHASE register (Addr 0x02) (see Figure 15).

POSITION

P[0]

CLI

tCLIDLY

1 PIXEL

PERIOD

P[12]

P[24]

P[36]

P[48] = P[0]

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6 ns TYP).

Figure 11. High Speed Clock Resolution from CLI Master Clock Input

CCD

SIGNAL

3

4

cds

(INTERNAL)

1

2

RG

5

6

H1

H2

PROGRAMMABLE CLOCK POSITIONS

1. RG RISING EDGE (FIXED EDGE AT 000000).

2. RG FALLING EDGE (RGNEGLOC (ADDR 0x03)).

3. SHP SAMPLE LOCATION (SHPLOC (ADDR 0x02)).

4. SHD SAMPLE LOCATION (SHDLOC (ADDR 0x02)).

5. H1 RISING EDGE LOCATION (H1POSLOC (ADDR 0x03))

6. H1 NEGATIVE EDGE LOCATION (FIXED AT (H1POSLOC + 24 STEPS)).

7. H2 IS ALWAYS THE INVERSE OF H1.

Figure 12. High Speed Clock Programmable Locations

–20–

REV. 0

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