AD9882A Просмотр технического описания (PDF) - Analog Devices
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AD9882A Datasheet PDF : 40 Pages
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Table 5. Analog Interface Pin List
Pin Type
Analog Video Inputs
External Sync/Clock
Sync Outputs
Voltage Reference Clamp Voltages
PLL Filter
Power Supply
Mnemonic
RAIN
GAIN
BAIN
HSYNC
VSYNC
SOGIN
HSOUT
VSOUT
SOGOUT
REFBYPASS
MIDBYPASS
FILT
VD
PVD
VDD
GND
Function
Analog input for Converter R
Analog input for Converter G
Analog input for Converter B
Horizontal SYNC input
Vertical SYNC input
Sync-on-green input
Hsync output (phase-aligned with DATACK)
Vsync output
Composite SYNC
Internal reference bypass
Internal midscale voltage bypass
Connection for external filter components for
internal PLL
Main power supply
PLL power supply (nominally 3.3 V)
Output power supply
Ground
AD9882A
Value
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
1.25 V
Pin
Number
70
65
59
79
80
64
88
87
89
73
74
48
3.15 V to 3.45 V
3.15 V to 3.45 V
2.2 V to 3.6 V
0V
PIN FUNCTION DETAIL: ANALOG INTERFACE
Inputs
RAIN—Analog Input for Red Channel
GAIN—Analog Input for Green Channel
BAIN—Analog Input for Blue Channel
High impedance inputs that accept the red, green, and blue
channel graphics signals, respectively. For RGB, the three
channels are identical and can be used for any colors, but colors
are assigned for convenient reference.
For proper 4:2:2 formatting in a YPbPr application, the Y must
be connected to the GAIN input, the Pb must be connected to the
BAIN input, and the Pr must be connected to the RAIN input.
They accommodate input signals ranging from 0.5 V to 1.0 V
full scale. Signals should be ac-coupled to these pins to support
clamp operation.
Hsync—Horizontal Sync Input
This input receives a logic signal that establishes the horizontal
timing reference and provides the frequency reference for pixel
clock generation. The logic sense of this pin is controlled by
Serial Register Bit 0x10, Bit 6 (Hsync polarity). Only the leading
edge of Hsync is used by the PLL; the trailing edge is used for
clamp timing. When Hsync polarity = 0, the falling edge of
Hsync is used. When Hsync polarity = 1, the rising edge is
active.
The input includes a Schmitt trigger for noise immunity, with a
nominal input threshold of 1.5 V.
Electrostatic discharge (ESD) protection diodes conduct heavily
if this pin is driven more than 0.5 V above the maximum
tolerance voltage (3.3 V) or more than 0.5 V below ground.
VSYNC—Vertical Sync Input
This is the input for vertical sync.
SOGIN—Sync-on-Green Input
This input is provided to assist with processing signals with
embedded sync, typically on the green channel. The pin is
connected to a high speed comparator with an internally
generated threshold, which is set by the value of Register 0x0F,
Bits 7 to 3.
When connected to an ac-coupled graphics signal with
embedded sync, it produces a noninverting digital output
on SOGOUT.
When not used, this input should be left unconnected. For
more details on this function and how it should be configured,
refer to the Sync-on-Green (SOG) section.
SOGOUT—Sync-on-Green Slicer Output
This pin can be programmed to produce either the output from
the sync-on-green slicer comparator or an unprocessed but
delayed version of the Hsync input. See Figure 20, the sync
processing block diagram, to view how this pin is connected.
Note that the output from this pin is the composite sync
without additional processing from the AD9882A.
Rev. 0 | Page 9 of 40
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