AD9874 Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

AD9874

IF Digitizing Subsystem

Analog Devices 

AD9874

Address

(Hex)

Bit

Breakdown

Width

Table I. SPI Address Map (continued)

Default Value Name

Description

CLOCK SYNTHESIZER

0x10

(5:0)

6

00

CKR(13:8) Reference Frequency Divisor (6 MSB of a 14-Bit Word).

0x11

0x12

(7:0)

(4:0)

8

0x38

5

0x00

CKR(7:0) Reference Frequency Divisor (8 LSB of a 14-Bit Word).

Default yields 300 kHz from fREF =16.8 MHz; Min = 3, Max = 16383.

CKN(12:8) Synthesized Frequency Divisor (5 MSB of a 13-Bit Word).

0x13

0x14

(7:0)

(6)

(5)

(4:2)

(1:0)

8

0x3C

1

0

1

0

3

0

2

3

CKN(7:0) Synthesized Frequency Divisor (8 LSB of a 13-Bit Word).

Default yields 300 kHz from fCLK = 18 MHz; Min = 3, Max = 8191.

CKF

CKINV

CKI

CKTM

Enable fast acquire.

Invert charge pump (0 = source current to increase VCO frequency).

Charge Pump Current in Normal Operation. IPUMP = (CKI + 1) ϫ 0.625 mA.

Manual Control of CLK Charge Pump (0 = Off, 1 = Up, 2 = Down,

3 = Normal).

0x15

(5:0)

6

0x0

CKFA(13:8) CK Fast Acquire Time Unit (6 MSB of a 14-Bit Word).

0x16

(7:0)

8

0x04

CKFA(7:0) CK Fast Acquire Time Unit (8 LSB of a 14-Bit Word).

SSI CONTROL

0x18

(7:0)

8

0x12

SSICRA SSI Control Register A. See Table III. (Default is FS and CLKOUT

three-stated.)

0x19

(7:0)

8

0x07

SSICRB SSI Control Register B. See Table III. (16-bit data, maximum drive strength.)

0x1A (3:0)

ADC TUNING

4

1

SSIORD Output Rate Divisor. fCLKOUT = fCLK/SSIORD.

0x1C (1)

(0)

1

0

1

0

TUNE_LC Perform tuning on the LC portion of the ADC (cleared when done).

TUNE_RC Perform tuning on the RC portion of the ADC (cleared when done).

0x1D (2:0)

3

0

CAPL1(2:0) Coarse Capacitance Setting for LC Tank (LSB is 25 pF, Differential).

0x1E (5:0)

6

0x00

CAPL0(5:0) Fine Capacitance Setting for LC Tank (LSB is 0.4 pF, Differential).

0x1F (7:0)

8

0x00

CAPR

Capacitance Setting for RC Resonator (64 LSB of Fixed Capacitance).

TEST REGISTERS AND SPI PORT READ ENABLE

0x37–

0x39

(7:0)

8

0x00

TEST

Factory Test Mode. Do not use.

0x3A

(7:4, 2:0) 7

0x0

(3)

1

0

TEST

Factory Test Mode. Do not use.

SPIREN Enable read from SPI port.

0x3B

(7:4, 2:0) 7

0x0

(3)

1

0

TEST

TRI

Factory Test Mode. Do not use.

Three-state DOUTB.

0x3C–

0x3E

(7:0)

1

0x00

TEST

Factory Test Mode. Do not use.

0x3F

(7:0)

8

Subject to

ID

Change

Revision ID (Read-Only); A write of 0x99 to this register is equivalent to

a power-on reset.

–14–

REV. A

Share Link: