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AD9864

IF Digitizing Subsystem

Analog Devices 

Table 9. Number of Bits per Frame for Different SSICR Settings

Number

of Bits

per

DW

EAGC

EFS

AAGC

Frame

0 (16 Bit) 0

0

NA

32

0

1

NA

49*

1

0

0

48

1

0

1

40

1

1

0

69*

1

1

1

59*

1 (24 Bit) 0

0

NA

48

0

1

NA

69*

1

0

0

64

1

0

1

56

1

1

0

89*

1

1

1

79*

*The number of bits per frame with embedded frame sync (EFS = 1); assume

at least 10 idle bits are desired.

The maximum SSIORD setting can be determined by the

equation

[ ] ( ) ( ) SSIORD ≤TRUNC DecimationFactor / No.of Bits per Frame (1)

where TRUNC is the truncated integer value.

Table 9 lists the number of bits within a frame for 16-bit and 24-

bit output data formats for all of the different SSICR settings. The

decimation factor is determined by the contents of Register 0x07.

An example helps illustrate how the maximum SSIORD setting

is determined. Suppose a user selects a decimation factor of 600

(Register 0x07, K = 0, M = 9) and prefers a 3-wire interface with

a dedicated frame sync (EFS = 0) containing 24-bit data

(DW = 1) with nonalternating embedded AGC data included

(EAGC = 1, AAGC = 0). Referring to Table 9, each frame will

consist of 64 data bits. Using Equation 1, the maximum

SSIORD setting is 9 (= TRUNC(600/64)). Thus, the user can

select any SSIORD setting between 1 and 9.

Figure 32 illustrates the output timing of the SSI port for several

SSI control register settings with 16-bit I/Q data, while Figure 33

shows the associated timing parameters. Note that the same

timing relationship holds for 24-bit I/Q data, with the excep-

tion that I and Q word lengths now become 24 bits. In the

default mode of operation, data is shifted out on rising edges of

CLKOUT after a pulse equal to a clock period is output from

the frame sync (FS) pin. As described above, the output data

consists of a 16-bit or 24-bit I sample followed by a 16-bit or

24-bit Q sample, plus two optional bytes containing AGC and

status information.

AD9864

tCLK

tHI tLOW

CLKOUT

tV

FS

tDV

DOUT

I15

I14

Figure 33. SSI Timing Parameters for SSI Timing*

*Timing parameters also apply to inverted CLKOUT or FS modes, with tDV

relative to the falling edge of the CLK and/or FS.

The AD9864 also provides the means for controlling the

switching characteristics of the digital output signals via the DS

(drive strength) field of the SSICRB. This feature is useful in

limiting switching transients and noise from the digital output

that may ultimately couple back into the analog signal path,

potentially degrading the AD9864’s sensitivity performance.

Figure 34 and Figure 35 show how the NF can vary as a func-

tion of the SSI setting for an IF frequency of 109.65 MHz. The

following two observations can be made from these figures:

1. The NF becomes more sensitive to the SSI output drive

strength level at higher signal bandwidth settings.

2. The NF is dependent on the number of bits within an SSI

frame that become more sensitive to the SSI output drive

strength level as the number of bits is increased. As a result,

one should select the lowest possible SSI drive strength set-

ting that still meets the SSI timing requirements.

10.0

9.8

9.6

9.4

9.2

9.0

8.8

8.6

8.4

8.2

8.0

1

16-BIT I/O DATA

24-BIT I/O DATA

16-BIT I/0 DATA

w/ DVGA ENABLED

2

3

4

5

6

7

SSI OUTPUT DRIVE STRENGTH SETTING

Figure 34. NF vs. SSI Output Drive Strength

(VDDx = 3.0 V, FCLK = 18 MSPS, BW = 10 kHz)

Rev. 0 | Page 21 of 44

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