AD9838 Просмотр технического описания (PDF) - Analog Devices

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AD9838

Mixed-Signal Front-End (MxFE) Processor for Broadband Communications

Analog Devices 

AD9838

FUNCTIONAL DESCRIPTION

SERIAL INTERFACE

The AD9838 has a standard 3-wire serial interface that is

compatible with the SPI, QSPI™, MICROWIRE®, and DSP

interface standards.

Data is loaded into the device as a 16-bit word under the control

of a serial clock input, SCLK. The timing diagram for this oper-

ation is given in Figure 4.

FSYNC is a level triggered input that acts as a frame synchroni-

zation and chip enable input. Data can be transferred into the

device only when FSYNC is low. To start the serial data transfer,

FSYNC should be taken low, observing the minimum FSYNC

to SCLK falling edge setup time, t7 (see Table 2). After FSYNC

goes low, serial data is shifted into the input shift register of the

device on the falling edges of SCLK for 16 clock pulses. FSYNC

can be taken high after the 16th falling edge of SCLK, observing

the minimum SCLK falling edge to FSYNC rising edge time, t8.

Alternatively, FSYNC can be kept low for a multiple of 16 SCLK

pulses and then brought high at the end of the data transfer. In

this way, a continuous stream of 16-bit words can be loaded

while FSYNC is held low; FSYNC goes high only after the 16th

SCLK falling edge of the last word loaded.

The SCLK can be continuous, or it can idle high or low between

write operations. In either case, it must be high when FSYNC

goes low (t12).

For an example of how to program the AD9838, see the AN-1070

Application Note on the Analog Devices, Inc., website. The

AD9838 has the same register settings as the AD9833/AD9834.

LATENCY PERIOD

A latency period is associated with each operation. When the

FSELECT and PSELECT pins change value, there is a pipeline

delay before control is transferred to the selected register.

When the t11 and t11A timing specifications are met (see Figure 3),

FSELECT and PSELECT have latencies of eight MCLK cycles.

When the t11 and t11A timing specifications are not met, the latency

is increased by one MCLK cycle.

Similarly, a latency period is associated with each asynchronous

write operation. If a selected frequency or phase register is

loaded with a new word, there is a delay of eight or nine MCLK

cycles before the analog output changes. The delay can be eight

or nine MCLK cycles, depending on the position of the MCLK

rising edge when the data is loaded into the destination register.

The negative transitions of the RESET and SLEEP pins are

sampled on the internal falling edge of MCLK. Therefore, they

also have a latency period associated with them.

CONTROL REGISTER

The AD9838 contains a 16-bit control register that allows the

user to configure the operation of the AD9838. All control bits

other than the MODE bit are sampled on the internal falling

edge of MCLK.

Figure 22 illustrates the functions of the control bits. Table 7

describes the individual bits of the control register. The different

functions and the various output options of the AD9838 are

described in more detail in the following sections.

To inform the AD9838 that the contents of the control register

will be altered, Bit D15 and Bit D14 must be set to 0, as shown

in Table 6.

Table 6. Control Register Bits

D15

D14

D13 to D0

0

0

Control bits

SLEEP12

SLEEP1

RESET

PHASE

ACCUMULATOR

(28-BIT)

MODE + OPBITEN

SIGN/PIB

OPBITEN

SIN

ROM

0

MUX

1

0

MUX

1

DIVIDE

BY 2

MSB

(LOW POWER)

10-BIT DAC

COMPARATOR

1

MUX

0

DIGITAL

OUTPUT

(ENABLE)

IOUT

IOUTB

VIN

SIGN BIT OUT

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6

D5

D4

D3 D2 D1 D0

0

0 B28 HLB FSEL PSEL PIN/SW RESET SLEEP1 SLEEP12 OPBITEN SIGN/PIB DIV2 0 MODE 0

Figure 22. Function of Control Bits

Rev. A | Page 17 of 32

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