AD9826 Просмотр технического описания (PDF) - Analog Devices

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Компоненты Описание

производитель

AD9826

Complete 16-Bit Imaging Signal Processor

Analog Devices 

AD9826

ANALOG

INPUTS

PIXEL n (R,G,B)

PIXEL (n+1)

CDSCLK1

CDSCLK2

ADCCLK

RED

PGA

OUT

GREEN

PGA

OUT

BLUE

PGA

OUT

RED (n–1)

GREEN (n–1)

BLUE (n–1)

RED (n)

GREEN (n)

BLUE (n)

RED (n+1)

GREEN (n+1)

BLUE (n+1)

MUX

OUT

GREEN (n–1)

BLUE (n–1)

RED (n)

GREEN (n)

BLUE (n)

RED (n+1)

GREEN (n+1)

OUTPUT

DATA

D<7:0>

R(n–2) G(n–2) G(n–2) B(n–2) B(n–2) R(n–1) R(n–1) G(n–1) G(n–1) B(n–1) B(n–1) R(n)

HIGH LOW

HB

LB

HB

LB

HB

LB

HB

LB

HB

BYTE BYTE

NOTES

1. THE MUX STATE MACHINE IS INTERNALLY RESET AT THE CDSCLK2 RISING EDGE.

2. EACH PIXEL IS SAMPLED AND AMPLIFIED BY THE PGAs AT CDSCLK2 FALLING EDGE.

3. AFTER CDSCLK2 RISING EDGE, THE NEXT ADCCLK RISING EDGE WILL ALWAYS SELECT RED PGA OUTPUT.

4. THE ADC SAMPLES THE MUX OUTPUT ON ADCCLK FALLING EDGES.

5. THE MUX SWITCHES TO THE NEXT PGA OUTPUT AT ADCCLK RISING EDGES.

R(n)

LB

G(n)

HB

G(n)

LB

Figure 11. Internal Timing Diagram for 3-Channel CDS Mode

–12–

REV. B

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