AD9393 Просмотр технического описания (PDF) - Analog Devices
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AD9393 Datasheet PDF : 40 Pages
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AD9393
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
A
D14
D15
D16
D18
D20
D22 DCLK HSOUT O/E SDA
B
D13
D12
D17
D19
D21
D23
DE VSOUT PD
SCL
C
D11
D10
GND GND
D
D9
D8
VDD
VDD
GND GND
GND FILT
E
D7
D6
F
D5
D4
GND
AD9393
VD
TOP VIEW
(Not to Scale)
GND
VD
GND GND
PVDD MDA
G
D3
D2
SCLK LRCLK DVDD DVDD
PVDD MCL
H
D1
D0
DDC_
SCL
GND
J
GND MCLK I2S3
I2S2
I2S1
I2S0
SPDIF
RTERM
DDC_
SDA
Rx2+
K
RxC– RxC+ GND Rx0– Rx0+ GND Rx1– Rx1+ GND Rx2–
Table 4. Complete Pin List
Pin No.
Mnemonic
Inputs
B9
PD
Digital Video Data Inputs
K5, K4, K8, K7, J10, K10
Digital Video Clock Inputs
K2, K1
Rx0+, Rx0−,
Rx1+, Rx1−,
Rx2+, Rx2−
RxC+, RxC−
Outputs
B6, A6, B5, A5, B4,
A4, B3, A3, A2, A1,
B1, B2, C1, C2, D1,
D2, E1, E2, F1, F2,
G1, G2, H1, H2
A7
D[23:0]
DCLK
A8
HSOUT
Figure 2. Pin Configuration
Description
Value
Power-Down Control. Power-Down Control/Three-State Control. The function 3.3 V CMOS
of this pin is programmable via Register 0x26[2:1].
Digital Input Channel x True/Complement. These six pins receive three pairs of TMDS
transition minimized differential signaling (TMDS ) pixel data (at 10× the pixel
rate) from a digital graphics transmitter.
Digital Data Clock True/Complement. This clock pair receives a TMDS clock at TMDS
1× pixel data rate.
Data Outputs. In RGB,
VDD
D[23:16] = Red[7:0]
D[15:8] = Green[7:0]
D[7:0] = Blue[7:0]
See Table 6
Data Output Clock. This is the main clock output signal used to strobe the
VDD
output data and HSOUT into external logic. Four possible output clocks can
be selected with Register 0x25[7:6]. These are related to the pixel clock (½×
pixel clock, 1× pixel clock, 2× frequency pixel clock, and a 90° phase shifted
pixel clock). They are produced by the internal PLL clock generator and are
synchronous with the pixel clock. The polarity of DCLK can also be inverted via
Register 0x24[0].
HSYNC Output Clock (Phase-Aligned with DCLK). Horizontal sync output. A
VDD
reconstructed and phase-aligned version of the HSYNC input. Both the
polarity and duration of this output can be programmed via serial bus
registers. By maintaining alignment with DCLK and data, data timing with
respect to horizontal sync can always be determined.
Rev. 0 | Page 6 of 40
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