AD9269(Rev0) Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

AD9269
(Rev.:Rev0)

16-Bit, 20/40/65/80 MSPS, 1.8 V Dual Analog-to-Digital Converter

Analog Devices 

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK+ 1

CLK– 2

SYNC 3

D0B (LSB) 4

D1B 5

D2B 6

D3B 7

D4B 8

D5B 9

DRVDD 10

D6B 11

D7B 12

D8B 13

D9B 14

D10B 15

D11B 16

PIN 1

INDICATOR

AD9269

TOP VIEW

(Not to Scale)

48 PDWN

47 OEB

46 CSB

45 SCLK/DFS

44 SDIO/DCS

43 ORA

42 D15A (MSB)

41 D14A

40 D13A

39 D12A

38 D11A

37 DRVDD

36 D10A

35 D9A

34 D8A

33 D7A

AD9269

NOTES

1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND

TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL

STRENGTH BENEFITS.

Figure 5. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic Description

0, EP

AGND

The exposed paddle is the only ground connection. It must be soldered to the PCB analog ground to

ensure proper functionality and heat dissipation, noise, and mechanical strength benefits.

1, 2

CLK+, CLK− Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.

3

SYNC

Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.

4 to 9, 11 to

18, 20, 21

D0B (LSB) to Channel B Digital Outputs. D0B is the LSB; D15B is the MSB.

D15B (MSB)

10, 19, 28, 37 DRVDD

Digital Output Driver Supply (1.8 V to 3.3 V).

22

ORB

Channel B Out-of-Range Digital Output.

23

DCOB

Channel B Data Clock Digital Output.

24

DCOA

Channel A Data Clock Digital Output.

25 to 27, 29 to D0A (LSB) to Channel A Digital Outputs. D0A is the LSB; D15A is the MSB.

36, 38 to 42 D15A (MSB)

43

ORA

Channel A Out-of-Range Digital Output.

44

SDIO/DCS SPI Data Input/Output (SDIO). Bidirectional SPI data I/O in SPI mode. 30 kΩ internal pull-down in SPI mode.

Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal

pull-up in non-SPI (DCS) mode.

45

SCLK/DFS SPI Clock (SCLK). Input in SPI mode. 30 kΩ internal pull-down.

Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down.

DFS high: twos complement output.

DFS low: offset binary output.

46

CSB

SPI Chip Select. Active low enable; 30 kΩ internal pull-up.

47

OEB

Digital Input. 30 kΩ internal pull-down.

Low: enable Channel A and Channel B digital outputs.

High: three-state outputs.

48

PDWN

Digital Input. 30 kΩ internal pull-down.

High: power down device.

Low: run device, normal operation.

Rev. 0 | Page 11 of 40

Share Link: