AD9238(RevA) Просмотр технического описания (PDF) - Analog Devices
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AD9238 Datasheet PDF : 24 Pages
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AD9238
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale input
frequency (fINPUT) due only to aperture jitter (tJ) can be calculated
with the following equation:
[ ] SNR degradation = 20 × log 10 1/2 × p × fINPUT × tJ
In the equation, the rms aperture jitter, tJ, represents the root-sum-
square of all jitter sources, which includes the clock input, analog
input signal, and ADC aperture jitter specification. Undersampling
applications are particularly sensitive to jitter.
For optimal performance, especially in cases where aperture jitter
may affect the dynamic range of the AD9238, it is important to
minimize input clock jitter. The clock input circuitry should use
stable references, for example using analog power and ground
planes to generate the valid high and low digital levels for the
AD9238 clock input. Power supplies for clock drivers should be sep-
arated from the ADC output driver supplies to avoid modulating
the clock signal with digital noise. Low jitter crystal controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other methods),
it should be retimed by the original clock at the last step.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9238 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is deter-
mined primarily by the strength of the digital drivers and the load
on each output bit. The digital drive current can be calculated by
IDRVDD = VDRVDD × CLOAD × fCLOCK × N
where N is the number of bits changing and CLOAD is the average
load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed grade
provides excellent performance while affording reduced power
consumption. Each speed grade dissipates a baseline power at low
sample rates that increases with clock frequency.
Either channel of the AD9238 can be placed into standby mode
independently by asserting the PWDN_A or PDWN_B pins.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
will result in a typical power consumption of 1 mW for the ADC.
Note that if DCS is enabled, it is mandatory to disable the clock
of an independently powered-down channel. Otherwise, sig-
nificant distortion will result on the active channel. If the clock
inputs remain active while in total standby mode, typical power
dissipation of 12 mW will result.
The minimum standby power is achieved when both channels are
placed into full power-down mode (PDWN_A = PDWN_B =
HI). Under this condition, the internal references are powered
down. When either or both of the channel paths are enabled after a
power-down, the wake-up time will be directly related to the
recharging of the REFT and REFB decoupling capacitors and to
the duration of the power-down. Typically, it takes approximately
5 ms to restore full operation with fully discharged 0.1 µF and
10 µF decoupling capacitors on REFT and REFB.
A single channel can be powered down for moderate power savings.
The powered-down channel shuts down internal circuits, but both
the reference buffers and shared reference remain powered. Because
the buffer and voltage reference remain powered, the wake-up
time is reduced to several clock cycles.
DIGITAL OUTPUTS
The AD9238 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to pro-
vide sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies that may affect converter performance. Applications
requiring the ADC to drive large capacitive loads or large fan-outs
may require external buffers or latches.
The data format can be selected for either offset binary or twos
complement. This is discussed later in the Data Format section.
TIMING
The AD9238 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propaga-
tion delay (tPD) after the rising edge of the clock signal. Refer to
Figure 1 for a detailed timing diagram.
A–1
A0
A1
A2
A3
A8
ANALOG INPUT
A7
ADC A
A4
A5
A6
B–1
B0
B1
B2
B3
B8
ANALOG INPUT
B7
ADC B
B4
B5
B6
CLK_A = CLK_B =
MUX_SELECT
B–8 A–7 B–7 A–6 B–6 A–5 B–5 A–4 B–4 A–3 B–3 A–2 B–2 A–1 B–1
A0
B0
A1
D0_A
–D11_A
tODF
tODR
Figure 7. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A,
CLK_B, and MUX_SELECT
–14–
REV. A
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