AD8110ASTZ Просмотр технического описания (PDF) - Analog Devices
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AD8110ASTZ Datasheet PDF : 21 Pages
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AD8110/AD8111
CE UPDATE CLK
1X
X
01
f
01
f
00
X
XX
X
DATA IN
X
Data i
D0 . . . D4,
A0 . . . A2
X
X
Table III. Operation Truth Table
SER/
DATA OUT RESET PAR Operation/Comment
X
X
Data i-40
1
NA in Parallel 1
Mode
X
1
X
0
X
No change in logic.
0
The data on the serial DATA IN line is loaded
into serial register. The first bit clocked into
the serial register appears at DATA OUT 40
clocks later.
1
The data on the parallel data lines, D0–D4, are
loaded into the 40-bit serial shift register loca-
tion addressed by A0–A2.
X
Data in the 40-bit shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
X
Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
D0
PARALLEL D1
DATA D2
(OUTPUT
ENABLE)
D3
D4
SER/PAR
DATA IN
(SERIAL)
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0
CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
DATA
OUT
CLK
CE
UPDATE
OUT0 EN
OUT1 EN
OUT2 EN
A0
OUT3 EN
A1
OUT4 EN
A2
OUT5 EN
OUT6 EN
OUT7 EN
RESET
(OUTPUT ENABLE)
LE D
OUT0
B0
Q
LE D
OUT0
B1
Q
LE D
OUT0
B2
Q
LE D
OUT0
B3
Q
LE D
OUT0
EN
CLR Q
LE D
OUT1
B0
Q
LE D
OUT6
EN
CLR Q
LE D
OUT7
B0
Q
LE D
OUT7
B1
Q
LE D
OUT7
B2
Q
LE D
OUT7
B3
Q
LE D
OUT7
EN
CLR Q
DECODE
128
SWITCH MATRIX
Figure 4. Logic Diagram
8
OUTPUT ENABLE
–6–
3&7#
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