AD8033ARZ-REEL71 Просмотр технического описания (PDF) - Analog Devices

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AD8033ARZ-REEL71

Low Cost, 80 MHz FastFET Op Amps

Analog Devices 

AD8033/AD8034

APPLICATIONS INFORMATION

HIGH SPEED PEAK DETECTOR

The low input bias current and high bandwidth of the AD8033/

AD8034 make the parts ideal for a fast settling, low leakage peak

detector. The classic fast-low leakage topology with a diode in

the output is limited to ~1.4 V p-p maximum in the case of the

AD8033/AD8034 because of the protection diodes across the

inputs, as shown in Figure 54.

VIN

~1.4V p-p MAX

AD8033/

AD8034

VOUT

Figure 54. High Speed Peak Detector with Limited Input Range

Using the AD8033/AD8034, a unity gain peak detector can

be constructed that captures a 300 ns pulse while still taking

advantage of the low input bias current and wide common-

mode input range of the AD8033/AD8034, as shown in Figure 55.

Using two amplifiers, the difference between the peak and the

current input level is forced across R2 instead of either amplifier’s

input pins. In the event of a rising pulse, the first amplifier

compensates for the drop across D2 and D3, forcing the voltage

at Node 3 equal to Node 1. D1 is off and the voltage drop across

R2 is zero. Capacitor C3 speeds up the loop by providing the

charge required by the input capacitance of the first amplifier,

helping to maintain a minimal voltage drop across R2 in the

sampling mode. A negative going edge results in D2 and D3

turning off and D1 turning on, closing the loop around the

first amplifier and forcing VOUT − VIN across R2. R4 makes

the voltage across D2 zero, minimizing leakage current and

kickback from D3 from affecting the voltage across C2.

The rate of the incoming edge must be limited so that the output

of the first amplifier does not overshoot the peak value of VIN

before the output of the second amplifier can provide negative

feedback at the summing junction of the first amplifier. This

is accomplished with the combination of R1 and C1, which

allows the voltage at Node 1 to settle to 0.1% of VIN in 270 ns.

The selection of C2 and R3 is made by considering droop

rate, settling time, and kickback. R3 prevents overshoot from

occurring at Node 3. The time constants of R1, C1 and R3, C2

are roughly equal to achieve the best performance. Slower time

constants can be selected by increasing C2 to minimize droop

rate and kickback at the cost of increased settling time. R1 and

C1 should also be increased to match, reducing the incoming

pulse’s effect on kickback.

VIN

R5

49.9Ω

+VS

1/2

R1

AD8034

1kΩ

C1

39pF/

120pF

–VS

C3

10pF

R2

1kΩ

D1

LS4148

C4

4.7pF

D3

LS4148

R4

6kΩ

D2

+VS

1/2

AD8034

LS4148

–VS

C2

180pF/

560pF

R3

200Ω

VOUT

Figure 55. High Speed, Unity Gain Peak Detector Using AD8034

Rev. D | Page 19 of 24

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