AD71028JST Просмотр технического описания (PDF) - Analog Devices

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AD71028JST

Dual Digital BTSC Encoder with Integrated DAC

Analog Devices 

AD71028

LRCLK

BCLK

SDATA

MSB

LEFT CHANNEL

RIGHT CHANNEL

LSB

MSB

1 /FS

LSB

Figure 7. Left-Justified Mode—16 Bits to 24 Bits per Channel

LRCLK

BCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

MSB

LSB

1 /FS

Figure 8. I2S Mode—16 Bits to 24 Bits per Channel

LRCLK

BCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

MSB

LSB

1 /FS

Figure 9. Right-Justified Mode—16 Bits to 24 Bits per Channel

LRCLK

BCLK

SDATA

MSB

LSB

1 /FS

MSB

LSB

Figure 10. DSP Mode—16 Bits to 24 Bits per Channel

NOTES

1. DSP mode does not identify the channel.

2. LRCLK normally operates at FS; in DSP mode, LRCLK operates at 2 × FS.

3. BCLK frequency is normally 64 × LRCLK but may be operated in burst mode.

Rev. 0 | Page 15 of 20

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