AD6122
MODCMREF
C15
0.1F
+15V
1
8
U2
SOIC PACKAGE
2 V–1
R7
3
7
A=1
50⍀
TO
IIPP
4 V–1 AD830
5
MODCMREF
+15V
C19
0.1F
1
8 U4
SOIC PACKAGE
2
3
V–1
7
A=1
R10
50⍀
TO
QIPP
4
V–1
AD830
5
ICH
R6
50⍀
–15V
+15V
C16
0.1F
C17
0.1F
QCH
R9
50⍀
–15V
+15V
C20
0.1F
C21
0.1F
1
2
3
MODCMREF
8
U3
V–1
7
A=1
R8
50⍀
TO
IIPN
4 V–1 AD830
5
1
2
MODCMREF 3
4
8
U5
V–1
7
A=1
V–1 AD830
5
R11
50⍀
TO
QIPN
–15V
C18
0.1F
–15V
C22
0.1F
TO
TXVCC
TO
DVCC
TO
IFVCC
C6
18pF
R1
10⍀
C13
0.01F
C5
18pF
C7
18pF
R2
10⍀
C12
0.01F
R3
10⍀
C14
0.01F
VREG OUT
–15V
MODCMREF
P1
P2
VPOS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
L1
470nH
VREG OUT
R4
10k⍀
FROM VPOS
2.9V–4.2V
R5
10k⍀
PD1
REFOUT
VGAIN
PD1
PD2
+15V
PD2
NOTES:
1. TO USE THE LDO REGULATOR, SHORT J2 AND OPEN J1.
2. TO BYPASS THE REGULATOR, SHORT J1 AND OPEN J2
3. TO CONNECT THE OUTPUT OF THE MODULATOR TO THE
INPUT OF THE IF AMP, SHORT J5 AND J6.
TO TEST THE MODULATOR AND THE IF AMP SEPARATELY,
OPEN J5 AND J6.
4.
INDICATES A 50⍀ TRACE.
Figure 34. Schematic Diagram of the Evaluation Board
REV. B
–19–