ACPL-7970-300E Просмотр технического описания (PDF) - Avago Technologies
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ACPL-7970-300E Datasheet PDF : 18 Pages
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Table 10. Input voltage with ideal corresponding density of 1s at modulator data output, and ADC code.
Analog Input
Voltage Input
Density of 1s
ADC Code (16-bit unsigned decimation)
Full-Scale Range
640 mV
+Full-Scale
+320 mV
100%
65,535
+Recommended Input Range
+200 mV
81.25%
53,248
Zero
0 mV
50%
32,768
–Recommended Input Range
-200 mV
18.75%
12,288
–Full-Scale
-320 mV
0%
0
Notes:
1. With bipolar offset binary coding scheme, the digital code begins with digital 0 at –FS input and increases proportionally to the analog input until
the full-scale code is reached at the +FS input. The zero crossing occurs at the mid-scale input.
2. Ideal density of 1s at modulator data output can be calculated with VIN/640 mV + 50%; similarly, the ADC code can be calculated with (VIN/640 mV)
× 65,536 + 32,768, assuming a 16-bit unsigned decimation filter.
Digital Filter
A digital filter converts the single-bit data stream from
the modulator into a multi-bit output word similar to
the digital output of a conventional A/D converter. With
this conversion, the data rate of the word output is also
reduced (decimation). A Sinc3 filter is recommended to
work together with the ACPL-7970. With 256 decimation
ratio and 16-bit word settings, the output data rate is 39
kHz (= 10 MHz/256). This filter can be implemented in an
ASIC, an FPGA or a DSP. Some of the ADC codes with cor-
responding input voltages are shown in Table 5.
ISOLATED
5V
ISOLATION
BARRIER
NON-
ISOLATED
5 V/3.3 V
INPUT
CURRENT
RSHUNT
VDD1
VIN+
0.1 µF
1 µF
VIN–
VDD2
VDD
SCLK
MCLK
CLOCK
0.1
1 µF
SDAT
µF
MDAT
DATA
CS
3-WIRE
SERIAL
INTERFACE
GND1
GND2
GND
SINC3 FILTER
GND1
ACPL-7970
GND2
Note: In applications, 1 mF/0.1 mF bypass capacitors are recommended to connect between pins VDD1 and GND1,
and between pins VDD2 and GND2 of the ACPL-7970.
Figure 17. Typical application circuit with a Sinc3 filter.
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