A8509GLBTR-T Просмотр технического описания (PDF) - Allegro MicroSystems

Номер в каталоге

Компоненты Описание

производитель

A8509GLBTR-T

Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver

Allegro MicroSystems 

A8509

Wide Input Voltage Range, High Efficiency

4-Channel Fault Tolerant LED Driver

Pin-out Diagrams

SENP 1

GATE 2

VDR 3

COMP 4

MODE 5

NC 6

NC 7

EN 8

PWM 9

FSET/SYNC 10

ISET 11

VDD 12

24 SENN

23 PGND

22 LED1

21 NC

20 LED2

19 AGND

18 AGND

17 LED3

16 LED4

15 VIN

14 OVP

13 FAULT

LB Package

SENN 1

24 PGND

SENP 2

23 NC

GATE 3

22 LED1

VDR 4

21 LED2

COMP 5

20 NC

MODE 6

PAD

19 AGND

EN 7

18 AGND

PWM 8

17 NC

FSET/SYNC 9

16 LED3

ISET 10

15 LED4

VDD 11

14 VIN

FAULT 12

13 OVP

LP Package

Terminal List Table

Name

Number

LB

LP

Function

AGND

18, 19 18, 19 LED ground.

COMP

4

5

Output of the error amplifier and compensation node. Connect a compensation network from this pin to ground.

EN

8

7

Enable for the A8509.

¯F¯ ¯A ¯U ¯¯L¯ ¯T¯

13

12

This pin is used to indicate a fault condition. Connect a pull-up resistor between this pin and the required logic

level voltage. The pin is an open drain type configuration that will be pulled low when a fault occurs.

FSET/SYNC 10

9

Frequency/synchronization pin. A resistor RFSET from this pin to ground sets the switching frequency. This pin

can also be used to synchronize two or more converters in the system.

GATE

2

3

Gate pin for driving external N-channel FET.

ISET

11

10

Connect the RISET resistor between this pin and ground to set the 100% LED current.

LED1

22

22

LED2

LED3

20

17

21

16

Connect the cathode of each LED string to these pins.

LED4

16

15

MODE

5

6

This pin is used to determine the mode of operation. MODE high tied to VDD allows parallel operation, and

MODE low is used for single IC operation.

NC

6, 7, 21 17, 20, 23 No connection.

OVP

14

13

This pin is used to sense an Overvoltage (OVP) condition. Connect the ROVP resistor from VOUT to this pin to

adjust the overvoltage protection.

PAD

n.a.

–

For TSSOP package, this exposed pad provides enhanced thermal dissipation. This pad must be connected to

the ground plane(s) of the PCB with at least 8 vias, directly in the PAD solder pad.

PGND

23

24

Power ground for the internal gate driver circuit.

PWM

9

8

PWM dimming pin. Used to control the LED intensity by using pulse width modulation. The typical PWM

dimming frequency is in the range of 100 to 1000 Hz.

SENN

24

1

Negative sense line for boost switch current sensing.

SENP

1

2

Positive sense line for boost switch current sensing.

VDD

12

11

Output of internal LDO regulator. Connect a 0.1 μF decoupling capacitor between this pin and ground.

VDR

3

4

Output of the gate driver bias voltage regulator. Connect a 1 μF decoupling capacitor between this pin and

ground.

VIN

15

14

Input power to the A8509.

Allegro MicroSystems, Inc.

4

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Share Link: