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A8509GLBTR-T

Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver

Allegro MicroSystems 

A8509

Wide Input Voltage Range, High Efficiency

4-Channel Fault Tolerant LED Driver

Frequency selection

The switching frequency on the boost regulator is set by con-

necting a resistor between the FSET/SYNC pin and ground.

The switching frequency range is 300 to 800 kHz, with example

values of:

RFSET Value

(kΩ)

7.5

10

Swtiching Frequency, fSW

(kHz)

800

600

VOUT

VFSET/SYNC

C2

IIN

C1

C3

IOUT

FSET/SYNC shorted to GND

The relationship of RFSET and fSW is shown in figure 9.

The FSET/SYNC pin has short-to-ground protection. If the

FSET/SYNC pin is held low for more than 4 μs typical, the

A8509 will stop switching and disable the LEDx pins (see figures

10 and 11). If the FSET/SYNC pin is released at any time after

7 μs, the A8509 will proceed to soft start but will not perform the

LED detection phase.

C4

t

Figure 10. Shutdown when the FSET/SYNC pin is shorted to ground;

shows VOUT (ch1, 10 V/div.), VFSET/SYNC (ch2, 1 V/div.), IIN (ch3, 2 A/div.),

and IOUT (ch4, 500 mA/div.), t = 200 μs/div.

VOUT

VFSET/SYNC

FSET/SYNC shorted to GND

Synchronization

The A8509 can also be synchronized by using an external clock

connected to the FSET/SYNC pin. The synchronization func-

tion of IC was designed to work with a push-pull type of clock

driver. The amplitude of the clock signal should be between

1.5 and 3.3 V. The synchronization clock should have duty

cycles that meet the minimum on/off times. Figure 12 shows the

timing for a synchronization clock into the A8509 at 800 kHz.

The 150 ns minimum on-time and 150 ns minimum off-time are

900

800

700

600

500

400

300

200

7

9

11

13

15

17

19

21

FSET Resistor Value, RFSET (kΩ)

Figure 9. Switching Frequency as determined by RFSET value.

C2

IIN

C1

C3

IOUT

C4

t

Figure 11. Zoomed-in view of figure 9, showing quick shutdown when

FSET/SYNC shorted to ground, preventing IC running at very high

frequency; shows VOUT (ch1, 10 V/div.), VFSET/SYNC (ch2, 1 V/div.),

IIN (ch3, 2 A/div.), and IOUT (ch4, 1 A/div.), t = 10 μs/div.

t PWSYNCON

150 ns

950 ns

T = 1.25 μs

150 ns

t PWSYNCOFF

Figure 12. SYNC pulse minimum on and off time

requirements, for an 800-kHz clock.

Allegro MicroSystems, Inc.

10

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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