74F114 Просмотр технического описания (PDF) - Philips Electronics
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74F114 Datasheet PDF : 6 Pages
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Philips Semiconductors
Dual J-K negative edge-triggered flip-flop
with common clock and reset
LOGIC DIAGRAM
Product specification
74F114
Q
Q
SD
RD
K
J
TO OTHER
CP
FLIP-FLOP
SF00113
FUNCTION TABLE
INPUTS
OUTPUTS
SD
RD
CP
J
K
Q
Q
OPERATING MODE
L
H
X
X
X
H
L Asynchronous Set
H
L
X
X
X
L
H Asynchronous Reset
L
L
X
X
X
H*
H* Undetermined *
H
H
↓
h
l
q
q Toggle
H
H
↓
l
h
L
H Load “0” (Reset)
H
H
↓
h
l
H
L Load “1” (Set)
H
H
↓
l
l
q
q Hold “no change”
H = High voltage level
h = High voltage level one setup time prior to High-to-Low clock transition
L = Low voltage level
l = Low voltage level one setup time prior to High-to-Low clock transition
q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition
X = Don’t care
↓ = High-to-Low clock transition
Asynchronous inputs: Low input to SD sets Q to High level, Low input to RD sets Q to Low level
Set and Reset are independent of clock
Simultaneous Low on both SD and RD makes both Q and Q High.
* = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
VCC
VIN
IIN
VOUT
IOUT
Tamb
Tstg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to VCC
40
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
1996 Mar 14
2
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