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74AVCH4T245 Просмотр технического описания (PDF) - NXP Semiconductors.

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74AVCH4T245 Datasheet PDF : 29 Pages
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NXP Semiconductors
6. Pinning information
6.1 Pinning
74AVCH4T245
VCC(A) 1
1DIR 2
2DIR 3
1A1 4
1A2 5
2A1 6
2A2 7
GND 8
16 VCC(B)
15 1OE
14 2OE
13 1B1
12 1B2
11 2B1
10 2B2
9 GND
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Fig 3. Pin configuration SOT109-1 (SO16)
74AVCH4T245
4-bit dual supply translating transceiver; 3-state
74AVCH4T245
VCC(A) 1
1DIR 2
2DIR 3
1A1 4
1A2 5
2A1 6
2A2 7
GND 8
16 VCC(B)
15 1OE
14 2OE
13 1B1
12 1B2
11 2B1
10 2B2
9 GND
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Fig 4. Pin configuration SOT403-1 (TSSOP16)
74AVCH4T245
terminal 1
index area
1DIR 2
2DIR 3
1A1 4
1A2 5
2A1 6
2A2 7
GND(1)
15 1OE
14 2OE
13 1B1
12 1B2
11 2B1
10 2B2
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Transparent top view
terminal 1
index area
74AVCH4T245
1OE 1
VCC(B) 2
VCC(A) 3
1DIR 4
12 2B2
11 GND
10 GND
9 2A2
(1) This is not a supply pin, the substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad
however if it is soldered the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration SOT763-1 (DHVQFN16)
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Transparent top view
Fig 6. Pin configuration SOT1161-1 (XQFN16)
74AVCH4T245
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 27 September 2011
© NXP B.V. 2011. All rights reserved.
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