73S8014R Просмотр технического описания (PDF) - Teridian Semiconductor Corporation

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73S8014R

Smart Card Interface

Teridian Semiconductor Corporation 

73S8014R Data Sheet

DS_8014R_012

Table 1 provides the 73S8014R pin names, pin numbers, type, equivalent circuits and descriptions.

Table 1: 73S8014R 20-Pin SOP Pin Definitions

Pin

Pin Name Number Type

Card Interface

I/O

14

IO

RST

15

O

CLK

17

O

PRES

19

I

VCC

18 PSO

GND

16 GND

Host Processor Interface

CMDVCC

6

I

5V/#V

7

I

Equivalent

Circuit

Description

Figure 14

Figure 13

Figure 12

Figure 16

Figure 11

–

Card I/O: Data signal to/from card. Includes an 11k pull-up

resistor to VCC.

Card reset: provides reset (RST) signal to card.

Card clock: provides clock signal (CLK) to card. The rate of this

clock is determined by the external crystal frequency or frequency

of the external clock signal applied on XTALIN and CLKDIV

selections.

Card Presence switch: active high indicates card is present.

Includes a high-impedance pull-down current source.

Card power supply – logically controlled by sequencer, output of

LDO regulator. Requires an external filter capacitor to the card

GND.

Card ground.

Figure 16

Figure 16

Command VCC (negative assertion): Logic low on this pin causes

the LDO regulator to ramp the VCC supply to the card and initiates

a card activation sequence, if a card is present.

5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and

card interface, logic low selects 3 volt operation. When the part is

to be used with a single card voltage, this pin should be tied to

either GND or VDD. However, it includes a high impedance pull-up

resistor to default this pin high (selection of 5V card) when not

connected. This pin shall not be changed when CMDVCC is low.

CLKDIV1

CLKDIV2

OFF

RSTIN

I/OUC

Sets the divide ratio from the XTAL oscillator (or external clock

input) to the card clock. These pins include a pull-up resistor for

CLKDIV1 and CLKLDIV2 to provide a default rate of divide by

two.

20

5

I

Figure 16

CLKDIV1

0

CLKDIV2

0

CLOCK RATE

XTALIN/8

0

1

XTALIN/4

1

1

XTALIN/2

1

0

XTALIN

Interrupt signal to the processor. Active Low - Multi-function

1

O Figure 10 indicating fault conditions and card presence. Open drain output

configuration – It includes an internal 20kΩ pull-up to VDD.

2

I

Figure 16 Reset Input: This signal is the reset command to the card.

3

IO

Figure 15

System controller data I/O to/from the card. Includes an 11K

pull-up resistor to VDD.

6

Rev. 1.0

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