GS8180Q36D Просмотр технического описания (PDF) - Giga Semiconductor

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производитель

GS8180Q36D

18Mb Burst of 2 SigmaQuad SRAM

Giga Semiconductor 

State Diagram

GS8180Q18/36D-200/167/133/100*

Power-Up

READ

Read NOP

READ

READ

Load New

Read Address

Always

(Fixed)

READ

DDR Read

WRITE

Write NOP

WRITE

Load New

Write Address

WRITE

Always

(Fixed)

DDR Write

WRITE

Notes:

1. Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+), next internal burst address is A0+1.

2. “READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is true for

“WRITE” and “WRITE”.

3. Read and write state machine can be active simultaneously.

4. State machine control timing sequence is controlled by K.

Rev: 2.03 10/2004

12/32

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2002, GSI Technology

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