GS8180Q18D-133(2002) Просмотр технического описания (PDF) - Giga Semiconductor

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производитель

GS8180Q18D-133
(Rev.:2002)

18Mb Σ2x2B2 SigmaQuad SRAM

Giga Semiconductor 

Preliminary

GS8180Q18/36D-200/167/133

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are

then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also

includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan

Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the

contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is

moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

JTAG TAP Block Diagram

0

Bypass Register

210

Instruction Register

TDI

TDO

ID Code Register

· 31 30 29 · · · 2 1 0

Boundary Scan Register

n· · ·· · · · · ·210

TMS

TCK

Test Access Port (TAP) Controller

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with

the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the

RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the

register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

Die

Revision

Code

Not Used

I/O

Configuration

GSI Technology

JEDEC Vendor

ID Code

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

x36 X X X X 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1

x18 X X X X 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1

Rev: 2.00f 6/2002

24/29

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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