DSP56F826PB Просмотр технического описания (PDF) - Freescale Semiconductor

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DSP56F826PB

16-bit Digital Signal Controllers

Freescale Semiconductor 

Synchronous Serial Interface (SSI) Timing

3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)

and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have

been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the

tables and in the figures.

4. 50% duty cycle

5. bl = bit length; wl = word length

STCK output

STFS (bl) output

STFS (wl) output

STXD

SRCK output

SRFS (bl) output

SRFS (wl) output

SRXD

tSCKW

tSCKH

tSCKL

tTFSBHM

tTFSBLM

tTFSWHM

tTXVM

tTXEM

First Bit

tTXNVM

tTFSWLM

Last Bit

tTXHIM

tRFSBHM

tRFBLM

tRFSWHM

tTSM

tSM

tHM

tTHM

Figure 3-24 Master Mode Timing Diagram

tRFSWLM

56F826 Technical Data, Rev. 14

Freescale Semiconductor

41

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