AM29LV001BB-55ECB Просмотр технического описания (PDF) - Advanced Micro Devices

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AM29LV001BB-55ECB

1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

Advanced Micro Devices 

Writing the reset command to the device resets the

device to reading array data. Address bits are don’t

care for this command.

The reset command may be written between the

sequence cycles in an erase command sequence

before erasing begins. This resets the device to

reading array data. Once erasure begins, however, the

device ignores reset commands until the operation is

complete.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the

sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to

reading array data (also applies during Erase

Suspend).

See “AC Characteristics” for parameters, and to Figure

14 for the timing diagram.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

Table 5 shows the address and data requirements.

This method is an alternative to that shown in Table 4,

which is intended for PROM programmers and requires

VID on address bit A9.

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence. A read cycle at address XX00h retrieves the

manufacturer code. A read cycle at address XX01h

returns the device code. A read cycle containing a

sector address (SA) and the address 02h returns 01h if

that sector is protected, or 00h if it is unprotected. Refer

to Table 2 for valid sector addresses.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Byte Program Command Sequence

The device programs one byte of data for each

program operation. The command sequence requires

four bus cycles, and is initiated by writing two unlock

write cycles, followed by the program set-up command.

The program address and data are written next, which

in turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or tim-

ings. The device automatically provides internally

generated program pulses and verify the programmed

cell margin. Table 5 shows the address and data

requirements for the byte program command

sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and

addresses are no longer latched. The system can

determine the status of the program operation by using

DQ7 or DQ6. See “Write Operation Status” for informa-

tion on these status bits.

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The Byte Program command

sequence should be reinitiated once the device has

reset to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1,” or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to

program bytes to the device faster than using the stan-

dard program command sequence. The unlock bypass

command sequence is initiated by first writing two

unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. The

device then enters the unlock bypass mode. A two-

cycle unlock bypass program command sequence is all

that is required to program in this mode. The first cycle

in this sequence contains the unlock bypass program

command, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Table 5 shows the requirements for the

command sequence.

During the unlock bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset

command sequence. The first cycle must contain the

data 90h; the second cycle the data 00h. Addresses

are don’t cares for both cycles. The device then returns

to reading array data.

14

Am29LV001B

September 26, 2002

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