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AM28F010A-90PI

1 megabit CMOS 12.0 volt, bulk erase flash memory with embedded algorithms

Advanced Micro Devices 

FLASH MEMORY PROGRAM/ERASE

OPERATIONS

Embedded Erase Algorithm

The automatic chip erase does not require the device

to be entirely pre-programmed prior to executing the

Embedded set-up erase command and Embedded

erase command. Upon executing the Embedded erase

command the device automatically will program and

verify the entire memory for an all zero data pattern.

The system is not required to provide any controls or

timing during these operations.

When the device is automatically verified to contain an

all zero pattern, a self-timed chip erase and verify be-

gin. The erase and verify operation are complete when

the data on DQ7 is “1" (see Write Operation Status sec-

tion) atwhich time the device returns to Read mode.

The system is not required to provide any control or

timing during these operations.

When using the Embedded Erase algorithm, the erase

automatically terminates when adequate erase margin

has been achieved for the memory array (no erase ver-

ify command is required). The margin voltages are in-

ternally generated in the same manner as when the

standard erase verify command is used.

The Embedded Erase Set-Up command is a command

only operation that stages the device for automatic

electrical erasure of all bytes in the array. Embedded

Erase Setup is performed by writing 30h to the com-

mand register.

To commence automatic chip erase, the command 30h

must be written again to the command register. The au-

tomatic erase begins on the rising edge of the WE and

terminates when the data on DQ7 is “1" (see Write Op-

eration Status section) at which time the device returns

to Read mode.

Figure 1 and Table 4 illustrate the Embedded Erase al-

gorithm, a typical command string and bus operation.

START

Apply VPPH

Write Embedded Erase Setup Command

Write Embedded Erase Command

Data# Poll from Device

Erasure Completed

Figure 1. Embedded Erase Algorithm

16778D-6

Table 4. Embedded Erase Algorithm

Bus Operations

Standby

Write

Read

Standby

Read

Command

Comments

Wait for VPP Ramp to VPPH (see Note)

Embedded Erase Setup Command Data = 30h

Embedded Erase Command

Data = 30h

Data# Polling to Verify Erasure

Compare Output to FFh

Available for Read Operations

Note: See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or

switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. Refer

to Functional Description.

12

Am28F010A

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