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MFRC52201HN1

Standard performance MIFARE and NTAG frontend

NXP Semiconductors. 

NXP Semiconductors

MFRC522

Standard performance MIFARE and NTAG frontend

16.1.3.5 Example: Output test signal RX data stream

Figure 32 shows the data stream that is currently being received. The TestSel2Reg

register’s TestBusSel[4:0] bits are set to 07h to enable test bus signals on pins D1 to D6;

see Section 16.1.2 on page 82. The TestSel1Reg register’s TstBusBitSel[2:0] bits are set

to 06h (pin D6 = s_data) and AnalogTestReg register is set to FFh (TstBusBit) which

outputs the received data stream on pins AUX1 and AUX2.

001aak601

(1)

(2)

(1) s_data (received data stream) (2 V/div).

(2) RF field.

Fig 32. Received data stream on pins AUX1 and AUX2

20 μs/div

16.1.3.6 PRBS

The pseudo-random binary sequences PRBS9 and PRBS15 are based on ITU-TO150

and are defined with the TestSel2Reg register. Transmission of either data stream is

started by the Transmit command. The preamble/sync byte/start bit/parity bit are

automatically generated depending on the mode selected.

Remark: All relevant registers for transmitting data must be configured in accordance with

ITU-TO150 before selecting PRBS transmission.

MFRC522

Product data sheet

COMPANY PUBLIC

All information provided in this document is subject to legal disclaimers.

Rev. 3.9 — 27 April 2016

112139

© NXP Semiconductors N.V. 2016. All rights reserved.

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