MFRC52201HN1 Просмотр технического описания (PDF) - NXP Semiconductors.

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MFRC52201HN1

Standard performance MIFARE and NTAG frontend

NXP Semiconductors. 

NXP Semiconductors

MFRC522

Standard performance MIFARE and NTAG frontend

001aak598

(1)

(2)

(3)

10 μs/div

(1) MinLevel (1 V/div) on pin AUX2.

(2) Corr1 (1 V/div) on pin AUX1.

(3) RF field.

Fig 29. Output test signals Corr1 on pin AUX1 and MinLevel on pin AUX2

16.1.3.3 Example: Output test signals ADC channel I and ADC channel Q

Figure 30 shows the channel behavior test signals ADC_I and ADC_Q on pins AUX1 and

AUX2, respectively. The AnalogTestReg register is set to 56h.

001aak599

(1)

(2)

(3)

5 μs/div

(1) ADC_I (1 V/div) on pin AUX1.

(2) ADC_Q (500 mV/div) on pin AUX2.

(3) RF field.

Fig 30. Output ADC channel I on pin AUX1 and ADC channel Q on pin AUX2

MFRC522

Product data sheet

COMPANY PUBLIC

All information provided in this document is subject to legal disclaimers.

Rev. 3.9 — 27 April 2016

112139

© NXP Semiconductors N.V. 2016. All rights reserved.

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