LTC6948IUFD-2 Просмотр технического описания (PDF) - Linear Technology

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LTC6948IUFD-2

Ultralow Noise 0.37GHz to 6.39GHz Fractional-N Synthesizer with Integrated VCO

Linear Technology 

LTC6948

Pin Functions

REF+, REF– (Pins 1, 28): Reference Input Signals. This

differential input is buffered with a low noise amplifier,

which feeds the reference divider. They are self-biased and

must be AC-coupled with 1µF capacitors. If used single-

ended with VREF+ ≤ 2.7VP-P, bypass REF– to GND with a

1µF capacitor. If used single-ended with VREF+ > 2.7VP-P,

bypass REF– to GND with a 47pF capacitor.

STAT (Pin 2): Status Output. This signal is a configurable

logical OR combination of the UNLOK, LOK, ALCHI, ALCLO,

THI, and TLO status bits, programmable via the STATUS

register. See the Operation section for more details.

CS (Pin 3): Serial Port Chip Select. This CMOS input initi-

ates a serial port communication burst when driven low,

ending the burst when driven back high. See the Operation

section for more details.

SCLK (Pin 4): Serial Port Clock. This CMOS input clocks

serial port input data on its rising edge. See the Operation

section for more details.

SDI (Pin 5): Serial Port Data Input. The serial port uses

this CMOS input for data. See the Operation section for

more details.

SDO (Pin 6): Serial Port Data Output. This CMOS three-

state output presents data from the serial port during a

read communication burst. Optionally attach a resistor of

>200k to GND to prevent a floating output. See the Ap-

plications Information section for more details.

LDO (Pin 7): Δ∑ Modulator LDO Bypass Pin. This pin

should be bypassed directly to the ground plane using a

low ESR (<0.8Ω) 0.1µF ceramic capacitor as close to the

pin as possible.

VD+ (Pin 8): 3.15V to 3.45V Positive Supply Pin for Serial

Port and Δ∑ Modulator Circuitry. This pin should be by-

passed directly to the ground plane using a 0.1µF ceramic

capacitor as close to the pin as possible.

MUTE (Pin 9): RF Mute. The CMOS active-low input mutes

the RF± differential outputs while maintaining internal bias

levels for quick response to deassertion.

GND (Pins 10, 17, 21, Exposed Pad Pin 29): Negative

Power Supply (Ground). These pins should be tied directly

to the ground plane with multiple vias for each pin. The

package exposed pad must be soldered directly to the PCB

land. The PCB land pattern should have multiple thermal

vias to the ground plane for both low ground inductance

and also low thermal resistance.

RF–, RF+ (Pins 11, 12): RF Output Signals. The VCO

output divider is buffered and presented differentially on

these pins. The outputs are open-collector, with 136Ω

(typical) pull-up resistors tied to VRF+ to aid impedance

matching. If used single-ended, the unused output should

be terminated to 50Ω. See the Applications Information

section for more details on impedance matching.

VRF+ (Pin 13): 3.15V to 3.45V Positive Supply Pin for

RF circuitry. This pin should be bypassed directly to the

ground plane using a 0.01µF ceramic capacitor as close

to the pin as possible.

BB (Pin 14): RF Reference Bypass. This output has a 2.5k

resistance and must be bypassed with a 1µF ceramic ca-

pacitor to GND. Do not couple this pin to any other signal.

TUNE (Pin 15): VCO Tuning Input. This frequency control

pin is normally connected to the external loop filter. See

the Applications Information section for more details.

For more information www.linear.com/LTC6948

6948f

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