OR2C10A3S208I-DB Просмотр технического описания (PDF) - Lattice Semiconductor

Номер в каталоге

Компоненты Описание

производитель

OR2C10A3S208I-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

Data Sheet

November 2006

ORCA Series 2 FPGAs

Programmable Logic Cells (continued)

The write address (WA[3:0]) and write data (WD[3:0])

are also latched by the RAM clock in order to simplify

Synchronous Memory Modes—SSPM and SDPM

the timing. Reading data from the RAM is done asyn-

chronously; thus, the read address (RA[3:0]) is not

The MA/MB asynchronous memory modes described

latched. The result from the read operation is placed on

previously allow the PFU to perform as a 16 x 4

the LUT outputs (F[3:0]). The F[3:0] data outputs can

(64 bits) single-port RAM. Synchronously writing to this

RAM requires the write-enable control signal to be

gated with the clock in another PFU to create a write

pulse. To simplify this functionality, the Series 2 devices

S contain a synchronous single-port memory (SSPM)

mode, where the generation of the write pulse is done

in each PFU.

E With SSPM mode, the entire LUT becomes a 16 x 4

RAM, as shown in Figure 14. In this mode, the input

IC ports are write enable (WE), write-port enable (WPE),

read/write address (A[3:0]), and write data (WD[3:0]).

D To synchronously write the RAM, WE (input into a4)

and WPE (input into either C0 or CIN) are latched and

V ANDed together. The result of this AND function is sent

E to a pulse generator in the LUT, which writes the RAM

synchronous to the RAM clock. This RAM clock is the

E same one sent to the PFU latches/FFs; however, if nec-

U essary, it can be programmably inverted.

D IN WE A4

DQ

WRITE PULSE

GENERATOR

T T WPE CIN, C0

DQ

C N A[3:0] A[3:0], B[3:0]

DQ

LE O WD[3:0] WD[3:0]

DQ

HLUTA

WR

F3

WA[3:0]

F2

RA[3:0]

WD[3:2]

HLUTB

WR

F1

be routed out of the PFU or sent to the latch/FF D[3:0]

inputs.

There are two ways to use the latches/FFs in conjunc-

tion with the SSPM. If the phase of the latch/FF clock

and the RAM clock are the same, only a read address

or write address can be supplied to the RAM that

meets the synchronous timing requirements of both

the RAM clock and latch/FF clock. Therefore, either a

write to the RAM or a read from the RAM can be done

in each clock cycle, but not both. If the RAM clock is

inverted from the latch/FF clock, then both a write to

the RAM and a read from the RAM can occur in each

clock cycle. This is done by adding an external write

address/read address multiplexer as shown in

Figure 15.

The write address is supplied on the phase of the clock

that allows for setup to the RAM clock, and the read

address is supplied on the phase of the clock that

allows the read data to be set up to the latch/FF clock.

If a higher-speed RAM is required that allows both a

read and write in each clock cycle, the synchronous

dual-port memory mode (SDPM) can be used, since it

does not require the use of an external multiplexer.

WRITE ADDRESS

1

READ ADDRESS

0

SSPM

WD

A

WE

WPE

RAM CLK

D

Q

E CWA[3:0]

S ISRA[3:0]

D WD[1:0]

F0

CLOCK

PFU

5-4642(F).r1

5-4644(F).r1

Figure 15. SSPM with Read/Write per Clock Cycle

Figure 14. SSPM Mode—16 x 4 Synchronous

Single-Port Memory

Lattice Semiconductor

15

Share Link: