AD7608 Просмотр технического описания (PDF) - Analog Devices
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AD7608 Datasheet PDF : 32 Pages
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AD7608
Data Sheet
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted. 1
Table 3.
Parameter
PARALLEL/SERIAL/BYTE MODE
tCYCLE
tCONV
tWAKE-UP STANDBY
tWAKE-UP SHUTDOWN
Internal Reference
External Reference
tRESET
tOS_SETUP
tOS_HOLD
t1
t2
t3
t4
t5 210F9F
t6
t7
PARALLEL/BYTE READ
OPERATION
t8
t9
t10
t11
t12
Limit at TMIN, TMAX
Min Typ Max
5
5
10.5
3.45 4 4.15
7.87
9.1
16.05
18.8
33
39
66
78
133
158
257
315
100
30
13
50
20
20
40
25
25
0
0.5
25
25
0
0
16
21
25
32
15
22
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ms
ms
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
1/throughput rate
Parallel mode, reading during or after conversion; or serial mode: VDRIVE =
3.3 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines
Serial mode reading during conversion; VDRIVE = 2.7 V
Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines
Conversion time
Oversampling off
Oversampling by 2
Oversampling by 4
Oversampling by 8
Oversampling by 16
Oversampling by 32
Oversampling by 64
STBYE rising edge to CONVST x rising edge; power-up time from
A
standby mode
STBYE rising edge to CONVST x rising edge; power-up time from
A
A
shutdown mode
STBYE rising edge to CONVST x rising edge; power-up time from
A
A
shutdown mode
RESET high pulse width
BUSY to OS x pin setup time
BUSY to OS x pin hold time
CONVST x high to BUSY high
Minimum CONVST x low pulse
Minimum CONVST x high pulse
BUSY falling edge to CSE falling edge setup time
A
A
Maximum delay allowed between CONVST A, CONVST B rising edges
Maximum time between last CSE rising edge and BUSY falling edge
A
A
Minimum delay between RESET low to CONVST x high
CSE to RDE setup time
A
A
A
A
CSE to RDE hold time
A
A
A
A
RDE low pulse width
A
A
VDRIVE above 4.75 V
VDRIVE above 3.3 V
VDRIVE above 2.7 V
VDRIVE above 2.3 V
RDE high pulse width
A
A
CSE high pulse width (see Figure 5); CSE and RDE linked
A
A
A
A
A
A
Rev. A | Page 6 of 32
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