EVAL-AD5754REBZ Просмотр технического описания (PDF) - Analog Devices

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EVAL-AD5754REBZ

Complete, Quad, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs

Analog Devices 

AD5724R/AD5734R/AD5754R

THEORY OF OPERATION

The AD5724R/AD5734R/AD5754R are quad, 12-/14-/16-bit,

serial input, unipolar/bipolar, voltage output DACs. They operate

from single supply voltages of +4.5 V to +16.5 V or dual supply

voltages of ±4.5 V to ±16.5 V. In addition, the devices have

software-selectable output ranges of +5 V, +10 V, +10.8 V, ±5 V,

±10 V, and ±10.8 V. Data is written to the AD5724R/AD5734R/

AD5754R in a 24-bit word format via a 3-wire serial interface.

The devices also offer an SDO pin to facilitate daisy chaining or

readback.

The AD5724R/AD5734R/AD5754R incorporate a power-on

reset circuit to ensure that the DAC registers power up loaded

with 0x0000. When powered on, the outputs are clamped to 0 V

via a low impedance path. The devices also feature on-chip

reference and reference buffers.

ARCHITECTURE

The DAC architecture consists of a string DAC followed by an

output amplifier. Figure 44 shows a block diagram of the DAC

architecture. The reference input is buffered before being applied

to the DAC.

REFIN

DAC REGISTER

REF (+)

RESISTOR

STRING

REF (–)

VOUTx

CONFIGURABLE

OUTPUT

AMPLIFIER

GND

OUTPUT

RANGE CONTROL

Figure 44. DAC Architecture Block Diagram

REFIN

R

R

R

TO OUTPUT

AMPLIFIER

R

R

Figure 45. Resistor String Structure

Data Sheet

The resistor string structure is shown in Figure 45. It is a string

of resistors, each of value R. The code loaded to the DAC register

determines the node on the string where the voltage is to be

tapped off and fed into the output amplifier. The voltage is tapped

off by closing one of the switches connecting the string to the

amplifier. Because it is a string of resistors, it is guaranteed

monotonic.

Output Amplifiers

The output amplifiers are capable of generating both unipolar

and bipolar output voltages. They are capable of driving a load

of 2 kΩ in parallel with 4000 pF to GND. The source and sink

capabilities of the output amplifiers can be seen in Figure 24.

The slew rate is 3.5 V/µs with a full-scale settling time of 10 µs.

Reference Buffers

The AD5724R/AD5734R/AD5754R can operate with either an

external or internal reference. The reference input has an input

range of 2 V to 3 V with 2.5 V for specified performance. This

input voltage is then buffered before it is applied to the DAC cores.

POWER-UP SEQUENCE

Because the DAC output voltage is controlled by the voltage

monitor and control block (see Figure 48), it is important to

power the DVCC pin before applying any voltage to the AVDD

and AVSS pins; otherwise, the G1 and G2 transmission gates are at

an undefined state. The ideal power-up sequence is in the

following order: GND, SIG_GND, DAC_GND, DVCC, AVDD,

AVSS, and then the digital inputs. The relative order of powering

AVDD and AVSS is not important, provided that they are powered

up after DVCC.

SERIAL INTERFACE

The AD5724R/AD5734R/AD5754R are controlled over a

versatile 3-wire serial interface that operates at clock rates up to

30 MHz. It is compatible with SPI, QSPI™, MICROWIRE, and

DSP standards.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the

device MSB first as a 24-bit word under the control of a serial

clock input, SCLK. The input register consists of a read/write

bit, three register select bits, three DAC address bits, and 16 data

bits. The timing diagram for this operation is shown in Figure 2.

Rev. G | Page 20 of 33

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