AD9361BBCZ Просмотр технического описания (PDF) - Analog Devices

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AD9361BBCZ

RF Agile Transceiver

Analog Devices 

Data Sheet

AD9361

Pin No.

C3

C4

C5, C6, D6, D5

D2

D3

D4, E4 to E6,

F4 to F6, G4

D7

Type1

O

I

I

I

I

O

I/O

Mnemonic

AUXDAC2

TEST/ENABLE

CTRL_IN0 to CTRL_IN3

VDDA1P3_RX_RF

VDDA1P3_RX_TX

CTRL_OUT0, CTRL_OUT1 to

CTRL_OUT3, CTRL_OUT6 to

CTRL_OUT4, CTRL_OUT7

P0_D9/TX_D4_P

D8

I/O

P0_D7/TX_D3_P

D9

I/O

P0_D5/TX_D2_P

D10

I/O

P0_D3/TX_D1_P

D11

I/O

P0_D1/TX_D0_P

D12, F7, F9, I

F11, G12, H7,

H10, K12

E1, F1

I

VSSD

RX2B_P, RX2B_N

E2

I

VDDA1P3_RX_LO

E3

I

VDDA1P3_TX_LO_BUFFER

E7

I/O

P0_D11/TX_D5_P

E8

I/O

P0_D8/TX_D4_N

E9

I/O

P0_D6/TX_D3_N

E10

I/O

P0_D4/TX_D2_N

E11

I/O

P0_D2/TX_D1_N

E12

I/O

P0_D0/TX_D0_N

Description

Auxiliary DAC 2 Output.

Test Input. Ground this pin for normal operation.

Control Inputs. Used for manual RX gain and TX attenuation control.

Receiver 1.3 V Supply Input. Connect to D3.

1.3 V Supply Input.

Control Outputs. These pins are multipurpose outputs that have programmable

functionality.

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D9, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D4_P) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D7, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D3_P) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D5, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D2_P) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D3, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D1_P) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D1, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D0_P) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

Digital Ground. Tie these pins directly to the VSSA analog ground on the printed

circuit board (one ground plane).

Receive Channel 2 Differential Input B. Each pin can be used as a single-ended

input or combined to make a differential pair. These inputs experience

degraded performance above 3 GHz. Tie unused pins to ground.

Receive LO 1.3 V Supply Input.

1.3 V Supply Input.

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D11, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 0. Alternatively, this pin (TX_D5_P) can function as part of the LVDS

6-bit TX differential input bus with internal LVDS termination.

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D8, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D4_N) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D6, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D3_N) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D4, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D2_N) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D2, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D1_N) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D0_N) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

Rev. F | Page 17 of 36

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