TMB22153AMS100 Просмотр технического описания (PDF) - Fairchild Semiconductor

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TMB22153AMS100

Demonstration Board for the TMC22x5yA Multistandard Digital Video Decoder

Fairchild Semiconductor 

TMB22153AMS100

Output Edge Connector Design notes:

Signal Flow FORWARD

PRELIMINARY INFORMATION

Y/Composite

LPF and

Clamp Circuit

Chrominance

BPF and

Clamp Circuit

TMC2242

10 bit

ADCs

Digital

LPFs

TMC2242

SW1

SW2

11

EPROM

FPGA

32 32

Decoder

Input Logic

DC Supply

11

TMC2072

TMC22153

TMC3003

SW1

32 32

+5V 0V -5V

Signal Flow BACKWARD

Low Quality

LPF

Low Quality

LPF

Low Quality

LPF

65-B2193-14

1. Boards with different revision letters may not be compatible; damage may occur if they are connected together.

2. XPXCK is a two times pixel clock fed BACKWARD

3. XHSYNC and XVSYNC are timing reference signals fed BACKWARD

4. The MASTER/SLAVE signal states if a board is a MASTER or a SLAVE board. This signal is fed FORWARD.

A MASTER board produces the PXCK, HSYNC, and VSYNC signals, and a SLAVE board expects to receive XPXCK,

XHSYNC, XVSYNC, etc.

5. XDIR is fed FORWARD and controls in which direction the XRS[3:0] data flows.

6. PGM_OUT negative going signal pulse for initiating programming of down stream boards, generated once the devices on

the board have been programmed. Care must be taken to ensure that multiple devices do not try to drive the RBUS at any

given time. The Minimum width of PGM_OUT is 1µS.

7. The RESET pin on the output edge connector should be connected directly to the RESET pin on the input connector.

A link should be used to connect any pulse to the RESET line.

8. The MASTER/SLAVE, XDIR, PGM_OUT and RESET pins on the output edge connector should be connected to +5V

through a 10k pull up resistor.

9. The CLAMP signal is fed BACKWARD from a MASTER to a SLAVE board. The CLAMP signal should not be fed

FORWARD.

16

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