Preliminary
SPHE8281D/Dx
Symbol
Pin No. I/O
Description
A_DATA[2] / GPIO
175
I/O Serial audio data output for channel 5/4 or GPIO
Priority selection
sft_cfg3[3]=1’b1
sft_cfg8[8]=1’b1
sft_cfg8[9]=1’b1
Function
Dir
A_DATA[2] (default)
O
ADC_MONO_PWAD
I
DAC_PDALL
I
(other)
GPIO[55]
I/O
A_DATA[3] / GPIO
A_LRCK/GPIO
176
I/O Serial audio data output for channel 7/6 or GPIO
Priority selection
sft_cfg3[4]=1’b1
sft_cfg8[8]=1’b1
sft_cfg8[9]=1’b1
Function
Dir
A_DATA[3] (default)
O
ADC_MONO_SPGA
I
DAC_TEST
I
(other)
GPIO[56]
I/O
177
I/O PCM data output L/R strobe
Priority selection
sft_cfg3[6]=1’b1
sft_cfg8[8]=1’b1
sft_cfg8[9]=1’b1
Function
dir
A_LRCK (default)
I/O
ADC_MONO_MODE1
I
DAC_UD
I
(other)
GPIO[57]
I/O
VSS_O6/ VSS_K6
A_BCK/GPIO
178
S
Kernel logic / I/O power shared ground supply #6
179
I/O PCM bit clock
Priority selection
Function
Dir
sft_cfg3[0]=1’b1
sft_cfg8[8]=1’b1
A_BCK (default)
I/O
ADC_MONO_MODE1
I
_1
sft_cfg8[9]=1’b1
DAC_BGPD
I
(other)
GPIO[58]
I/O
A_XCK/GPIO
180
I/O Audio over-sampling clock
Priority selection
sft_cfg3[9]=1’b1
sft_cfg8[8]=1’b1
sft_cfg8[9]=1’b1
(other)
Function
Dir
A_XCK (default)
I/O
ADC_MONO_MODE2
I
DAC_CLK
I
GPIO[59]
I/O
UA0_RX/GPIO
181
I/O UART #0 data receive or GPIO
Priority selection
sft_cfg2[3:2] =2’b01
sft_cfg3[13:12]=2’b01
sft_cfg4[15:13]=3’b011
Function
Dir
UART0_RX (default)
I
TV_HSYNC
I/O
HSYNC_PC
O
(other)
GPIO[60]
I/O
© Sunplus Confidential
19
Contents are subject to change without Notice
MAY. 19, 2005
Preliminary Version: 0.1