S5L9290X Просмотр технического описания (PDF) - Samsung

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производитель

S5L9290X

DIGITAL SIGNAL PROCESSOR FOR CDP

Samsung 

PRELIMINARY

S5L9290X

DIGITAL SIGNAL PROCESSOR FOR CDP

$98 Command

Control cycle and gain control in CLV speed mode

Command

CLV gain

control

Address

10011000

($98)

D7

OVSPL

D6

WBN

D5

WPN

Data

D4

D3

D2

-

OVSPL

MS

WB

OVSPL (option)

Output by oversampling the CLV output (SMDP, SMDS) cycle by 7.35kHz *4

H : Over-sampling Enable,

L : Over-sampling Disable

WBN (option)

Bottom Hold Cycle control in the CLV speed mode

H : RFCK/64,

L : determined by WB

WPN (option)

Peak Hold cycle control in the CLV speed mode

H : RFCK/8,

L : determined by WP

OVSPL_MS (option)

SMDS output mode setting at over-sampling enable

H : PWM (H, L),

L : Tri-State (H, Hi-Z, L)

WB

Bottom Hold cycle control in the CLV speed mode

H : RFCK/16,

L : RFCK/32

WP

Peak Hold cycle control in the CLV speed mode

H : RFCK/2,

L : RFCK/4

GAIN

SMDS output gain control in the CLV speed mode

H : 0dB,

L : -12dB

D1

D0

WP

GAIN

20

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