S25FL016A Просмотр технического описания (PDF) - Spansion Inc.
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S25FL016A
Spansion Inc.
S25FL016A Datasheet PDF : 36 Pages
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Data Sheet
7.6
Data Protection Modes
Spansion SPI Flash memory devices provide the following data protection methods:
The Write Enable (WREN) command: Must be written prior to any command that modifies data. The
WREN command sets the Write Enable Latch (WEL) bit. The WEL bit resets (disables writes) on power-up
or after the device completes the following commands:
– Page Program (PP)
– Sector Erase (SE)
– Bulk Erase (BE)
– Write Disable (WRDI)
– Write Status Register (WRSR)
Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the
memory array that can be read but not programmed or erased. Table 7.1 shows the sizes and address
ranges of protected areas that are defined by Status Register bits BP2:BP0.
Hardware Protected Mode (HPM): The Write Protect (W#) input and the Status Register Write Disable
(SRWD) bit together provide write protection.
Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands
consist of a clock pulse count that is a multiple of eight before executing them.
Table 7.1 S25FL016A Protected Area Sizes
Status Register
Block Protect Bits
BP2 BP1 BP0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Protected
Address Range
None
1F0000h–1FFFFFh
1E0000h–1FFFFFh
1C0000h–1FFFFFh
180000h–1FFFFFh
100000h–1FFFFFh
000000h–1FFFFFh
000000h–1FFFFFh
Memory Array
Protected
Sectors
Unprotected
Address Range
(0)
000000h–1FFFFFh
(1) SA31
000000h–1EFFFFh
(2) SA31:SA30
000000h–1DFFFFh
(4) SA31:SA28
000000h–1BFFFFh
(8) SA31:SA24
000000h–17FFFFh
(16) SA31:SA16 000000h–0FFFFFh
(32) SA31:SA0
None
(32) SA31:SA0
None
Unprotected
Sectors
SA31:SA0
SA30:SA0
SA29:SA0
SA27:SA0
SA23:SA0
SA15:SA0
None
None
Protected
Portion of
Total Memory
Area
0
1/32
1/16
1/8
1/4
1/2
All
All
7.7
Hold Mode (HOLD#)
The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write
Status Register, program or erase operation that is currently in progress.
The Hold mode starts on the falling edge of HOLD# if SCK is also low (see Figure 7.1, standard use). If the
falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling edge of
SCK (non-standard use).
The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge
of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-
standard use) See Figure 7.1.
The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the
Hold mode.
CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains
unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the
device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,
followed by driving CS# low.
January 7, 2008 S25FL016A_00_C3
S25FL016A
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