CY7C1318V18 Просмотр технического описания (PDF) - Cypress Semiconductor

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Компоненты Описание

производитель

CY7C1318V18

18-Mb DDR-II SRAM Two-word Burst Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1316V18

CY7C1318V18

CY7C1320V18

Identification Register Definitions

Instruction Field

Revision Number (31:29)

Cypress Device ID (28:12)

Cypress JEDEC ID (11:1)

ID Register Presence (0)

Value

CY7C1316V18

CY7C1318V18

CY7C1320V18

Description

000

000

000

Version number.

11010100010000101 11010100010010101 11010100010100101 Defines the type of SRAM.

00000110100

00000110100

00000110100 Allows unique identification of

SRAM vendor.

1

1

1

Indicate the presence of an ID

register.

Scan Register Sizes

Register Name

Instruction

Bypass

ID

Boundary Scan

Bit Size

3

1

32

107

Instruction Codes

Instruction

EXTEST

IDCODE

SAMPLE Z

RESERVED

SAMPLE/PRELOAD

RESERVED

RESERVED

BYPASS

Code

Description

000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and

TDO. This instruction is not 1149.1 compliant. The EXTEST command implemented by these

devices will NOT place the output buffers into a high-Z condition. If the output buffers

need to be in high-Z condition, this can be accomplished by deselecting the Read port.

001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.

The SAMPLE Z command implemented by these devices will place the output buffers into

a high-Z condition.

011 Do Not Use: This instruction is reserved for future use.

100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and

TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload

function and is therefore not 1149.1 compliant.

101 Do Not Use: This instruction is reserved for future use.

110 Do Not Use: This instruction is reserved for future use.

111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

Boundary Scan Order

Bit #

0

1

2

3

4

5

6

7

8

9

10

Bump ID

6R

6P

6N

7P

7N

7R

8R

8P

9R

11P

10P

Boundary Scan Order (continued)

Bit #

11

12

13

14

15

16

17

18

19

20

21

Bump ID

10N

9P

10M

11N

9M

9N

11L

11M

9L

10L

11K

Document #: 38-05177 Rev. *A

Page 21 of 24

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