MN838850 Просмотр технического описания (PDF) - Panasonic Corporation
Номер в каталоге
Компоненты Описание
производитель
MN838850 Datasheet PDF : 26 Pages
| |||
Color TFT LCD Driver
MN838850
s Electrical Characteristics (continued)
3. DC Characteristics at DVDD = 2.7 V to 3.6 V, AVDD = 14.5 V to 15.5 V, AVSS = DVSS = 0 V, Ta = −20 °C to +75 °C (continued)
Parameter
Symbol
Conditions
Min Typ Max Unit
3) Pull-down resistor pin TEST
High-level input voltage
VIH3
Low-level input voltage
VIL3
Input leakage current
ILI3
Pull-down resistance
RPD
4) Reference voltage input pins VOPU, VOPL
0.7 × DVDD
DVDD
V
0
0.3× DVDD V
−10
10
µA
40 100 350 kΩ
Input current
IVOP
−100
100
µA
5) Analog output pins Y1 to Y384
Output current *4
Output voltage difference *5
IVOH
IVOL
∆VO
VX = 15 V, VOUT = 14 V,
AVDD = 15 V, DVDD = 3.3 V
VX = 0.0 V, VOUT = 1.0 V,
AVDD = 15 V, DVDD = 3.3 V
AVDD = 15 V, DVDD = 3.3 V
− 0.5 − 0.2 mA
0.2
0.5
±4 ±20 mV
6) Analog output pin (Y1 to Y384) output voltage range
Operating voltage range *6
VO
AVSS+0.2 AVDD− 0.2 V
Note) 1. *1: The standard conditions are as follows. A clock frequency of 50 MHz, a raster period of 15 µs, the data pattern
fixed at FF, the POL level switched between high and low at each raster period, INV1 and INV2 held fixed at the
low level, and each of VREF0 to VREF9 held fixed at its respective levels.
*2: The maximum conditions are as follows. A clock frequency of 50 MHz, a raster period of 15 µs, the data pattern
switches between FF and 00 on each clock cycle, the POL level switched between high and low at each raster
period, INV1 and INV2 held fixed at the low level, and each of VREF0 to VREF9 held fixed at its respective levels.
*3: The loads on the analog output pins (Y1 to Y384) are shown below. The values of the components in the load
circuit are subject to change.
AVDD
DVDD
ISS3
ISS4
ISS2
ISS1
A
A
AVDD
DVDD
DVSS
DUT
Y1
Y2
·······
Y384
5 kΩ
75 pF
75 pF
AVSS
AVSS
0V
DUT : Device Under Test
*4: The VX are the output voltages from the analog output pins Y1 to Y384.
The VOUT are the voltages applied to the analog output pins Y1 to Y384.
*5: The standard conditions apply when the output voltages are at the same voltage as VOPL and VOPU.
*6: Set up VREF0 to VREF9, VOPU, and VOPL so that the output voltages never exceed the output voltage range
listed above.
2. The following formula expresses the power dissipation when the loads described in *3 above are attached.
ISS1 × AVDD + ISS3 × DVDD
Replace ISS1 in the above formula with the value of ISS2 to calculate the power dissipation when there is no load.
3. The supply current in the no load state is provided for reference purposes and is not guaranteed.
23
Share Link: 