MAX9268GCM/V Просмотр технического описания (PDF) - Maxim Integrated
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MAX9268GCM/V Datasheet PDF : 35 Pages
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Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
AC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
LVDS Output Pulse Position
fTXCLKOUT_
=
12.5MHz
N/7 x tCLK
- 250
N/7 x
tCLK
N/7 x tCLK
+ 250
N = 0 to 6, tCLK =
1/fTXCLKOUT_,
fTXCLKOUT_ = 33MHz
N/7 x tCLK N/7 x N/7 x tCLK
- 200 tCLK + 200
tPPOSN fTXCLKOUT_ =
ps
104MHz
(Figure 7)
fTXCLKOUT_ = 78MHz
N/7 x tCLK N/7 x N/7 x tCLK
- 125 tCLK + 125
fTXCLKOUT_ = 104MHz
N/7 x tCLK N/7 x N/7 x tCLK
- 100 tCLK + 100
LVDS Output Enable Time
tLVEN
From the last bit of the enable UART
packet to VOS = 1125mV
100
Fs
LVDS Output Disable Time
Deserializer Delay
tLVDS
tSD
From the last bit of the enable UART
packet to VOS = 0V
Figure 8 (Note 4)
100
Fs
3540 Bits
Reverse Control-Channel Output
Rise Time
tR
No forward-channel data transmission
(Figure 1)
180
400
ns
Reverse Control-Channel Output
Fall Time
tF
No forward-channel data transmission
(Figure 1)
180
400
ns
Lock Time
Power-Up Time
I2S OUTPUT TIMING
WS Jitter
SCK Jitter
Audio Skew Relative to Video
SCK, SD, WS Rise-and-Fall Time
tLOCK
tPU
tAJ-WS
tAJ-SCK
tASK
tR, tF
Figure 9
Figure 10
tWS = 1/fWS,
rising (falling)
edge to falling
(rising) edge
(Note 5)
fWS = 48kHz or 44.1kHz
fWS = 96kHz
fWS = 192kHz
nWS = 16 bits, fWS =
tSCK = 1/fSCK,
rising edge to
rising edge
48kHz or 44.1kHz
nWS = 24 bits, fWS =
96kHz
nWS = 32 bits,
fWS = 192kHz
Video and audio synchronized
20% to 80%
CL = 10pF, DCS = 1
CL = 5pF, DCS = 0
3.6
ms
4.1
ms
0.4e-3 0.5e-3
x tWS x tWS
0.8e-3
x tWS
1e-3
x tWS
ns
1.6e-3 2e-3
x tWS x tWS
13e-3 16e-3
x tSCK x tSCK
39e-3 48e-3
ns
x tSCK x tSCK
0.1
0.13
x tSCK x tSCK
3 x tWS 4 x tWS Fs
0.3
3.1
ns
0.4
3.8
SD, WS Valid Time Before SCK
tDVB
tSCK = 1/fSCK (Figure 11)
0.35 x 0.5 x
tSCK tSCK
ns
SD, WS Valid Time After SCK
tDVA
tSCK = 1/fSCK (Figure 11)
0.35 x 0.5 x
tSCK tSCK
ns
Note 2: Minimum IIN due to voltage drop across the internal pullup resistor.
Note 3: Measured in serial link bit times. Bit time = 1/(30 x fTXCLKOUT_) for BWS = GND. Bit time = 1/(40 x fTXCLKOUT_) for VBWS =
VIOVDD.
Note 4: Rising to rising-edge jitter can be twice as large.
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