KS8695P Просмотр технического описания (PDF) - Micrel

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Компоненты Описание

производитель

KS8695P

Integrated Multi-Port PCI Gateway Solution

Micrel 

Micrel, Inc.

KS8695P

Following pins have second function as factory test of chip.

Configuration

Chip Test Enable

Pin Name

TESTEN

Pin #

F17

ERWEN0/TESTACK

M17

ERWEN1/TESTREQB

N17

ERWEN2/TESTREQA

P17

ERWEN3/TICTESTTENN R17

UCTSN/BISTEN

M14

UDCDN/SCANEN

L15

URIN/TSTRST

L14

TEST1

M4

TEST2

F4

Setting

‘0’ = normal operation

‘1’ = factory reserved. Used for factory test of

chip and affects all signals listed in this table.

Table 2. Configuration Pins

Reset

The KS8695P has a single reset input that can be driven by a system reset circuit or a simple power on reset circuit. The

KS8695P also features a reset output (WRSTO) that can be used to reset other devices in the system. WRSTO can be

configured as either an active high reset or an active low reset through a strap-in option on pin U17, as shown in Table 1.

The KS8695P also has a built in watchdog timer. When the watchdog timer is programmed and the timer setting expires,

the KS8695P resets itself and also asserts WRSTO to reset the other devices in the system. Figure 4 shows a typical

system using the KS8695P WRSTO as the system reset.

Reset Circuit Diagram

Figure 4. Example of a Reset Circuit

VCC

D1

KS8695P

RST

R

10k

C

D2

10µF

CPU/FPGA

RST_OUT_n

Figure 5. Recommended Circuit for Interfacing with CPU/FPGA Reset

At power-on-reset, R, C,and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from

CPU/FPGA provides warm reset after power up.

May 2006

19

M9999-051806

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