Pin
No.
Symbol
20 Y_IN
21 CB_IN
22 CR_IN
23 F0
24 F1
CXA2150AQ
Equivalent circuit
VCC_OUT
VCC5
100k
500
20
2k
21
22
80k
Description
External Y, Cb and Cr inputs
Input 0.7Vp-p, 100 IRE Y, Cb and Cr
signals (when Cb and Cr are at 100%
color bar) via a capacitor.
The pedestal is clamped to 3.5V.
∗ Input voltage range: less than 5V
VCC9
2k
23
24
120k
VREG5
75k
75k
3.75V
Horizontal free-running frequency
setting
(See Table 1 on page 44.)
25 SDA
26 SCL
27 SCP
VCC5
4k
25
I2C bus protocol SDA (Serial Data)
input
VIH ≥ 3V
VIL ≤ 1.5V
2.5V
VOL ≤ 0.6V
VCC5
4k
26
I2C bus protocol SCL (Serial Clock)
input
VIH ≥ 3V
VIL ≤ 1.5V
2.5V
VCC9
150
27
1.2k
1k
34k
–7–
Sand castle pulse output
The approximately 0 to 5V CLP pulse
is output superimposed on the
approximately 0 to 2.5V HBLK and
VBLK pulses.
∗ Allowable load current: –0.5 to +2mA