AI2410 Просмотр технического описания (PDF) - A1 PROs co., Ltd.
Номер в каталоге
Компоненты Описание
производитель
AI2410 Datasheet PDF : 27 Pages
| |||
Signal Processor for Single-Chip CCD B/W Camera
Ai2410
External Synchronization
1. External/Internal Sync Selection
External or internal synchronization is selected automatically by a combination of 3 pins (VR/SYNC,
HPLL and ESYNC) to which the sync signal is input externally. The table below shows the input pattern
combinations.
Input
VR/SYNC pin: SYNC signal VR/SYNC pin: VD signal VR/SYNC pin: SYNC signal
pattern HPLL pin : Open
HPLL pin : HD signal HPLL pin : Open
EXT pin
ESYNC pin : Open
High
ESYNC pin : VDD
High
ESYNC pin : Open
Low
Output
Sync state External sync
External sync
Internal sync
Note ) Operation is possible even if the VD cycle of the VD input in the VD/HD sync mode is longer
than normal.
The EXT pin is the external/internal sync identification signal output pin. This output signal can be used
as the signal to select LC oscillation for expanding the lock range for external synchronization or the
oscillator for improving the oscillation accuracy for internal synchronization.
2. Reset Operation
SYNC synchronization
The VR1 signal component is extracted from the SYNC signal supplied externally and, for EIA,V reset
is performed so that the VD pulse falls at the count of 259H (262.5-3.5H) from the fall of the VR1 pulse.
For CCIR, it is reset in such a way that the VD pulse falls at the count of 309H(312.5-3.5H).For these
reasons, it is a prerequisite that the SYNC signal input comply with the EIA or CCIR standard.
VD/HD synchronization
V reset is performed so that the VD pulse 1H later after detecting the fall of the VD(VDR) pulse
supplied externally. Therefore, this enables V reset operation regardless of the field line number. The
phase difference between the VDRpulse and HD pulse which is locked horizontally at PLL circuit
identifies whether the field is odd or even. (VDR must have a pulse width of 2H or more.)
15
Preliminary
Share Link: 