M7A3P1000-QN144I Просмотр технического описания (PDF) - Actel Corporation

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M7A3P1000-QN144I

ProASIC3 Flash Family FPGAs with Optional Soft ARM® Support

Actel Corporation 

ProASIC3 DC and Switching Characteristics

Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Applicable to Standard Plus I/O Banks

Single-Ended

VMV (V)

Static Power

PDC2 (mW) 1

Dynamic Power

PAC9 (µW/MHz) 2

3.3 V LVTTL / 3.3 V LVCMOS

3.3

–

16.72

2.5 V LVCMOS

2.5

–

5.14

1.8 V LVCMOS

1.8

–

2.13

1.5 V LVCMOS (JESD8-11)

1.5

–

1.48

3.3 V PCI

3.3

–

18.13

3.3 V PCI-X

3.3

–

18.13

Notes:

1. PDC2 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VCC and VMV.

Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings

Applicable to Standard I/O Banks

Single-Ended

VMV (V)

Static Power

PDC2 (mW) 1

Dynamic Power

PAC9 (µW/MHz) 2

3.3 V LVTTL / 3.3 V LVCMOS

3.3

–

16.79

2.5 V LVCMOS

2.5

–

5.19

1.8 V LVCMOS

1.8

–

2.18

1.5 V LVCMOS (JESD8-11)

1.5

–

1.52

Notes:

1. PDC2 is the static power (where applicable) measured on VMV.

1. PAC9 is the total dynamic power measured on VCC and VMV.

v1.3

2-7

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