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ADXL345BCCZ

3-Axis, ±2 g/±4 g/±8 g/±16 g Digital Accelerometer

Analog Devices 

ADXL345

Data Sheet

INTERRUPTS

The ADXL345 provides two output pins for driving interrupts:

INT1 and INT2. Both interrupt pins are push-pull, low impedance

pins with output specifications shown in Table 13. The default

configuration of the interrupt pins is active high. This can be

changed to active low by setting the INT_INVERT bit in the

DATA_FORMAT (Address 0x31) register. All functions can be

used simultaneously, with the only limiting feature being that

some functions may need to share interrupt pins.

Interrupts are enabled by setting the appropriate bit in the

INT_ENABLE register (Address 0x2E) and are mapped to

either the INT1 pin or the INT2 pin based on the contents of the

INT_MAP register (Address 0x2F). When initially configuring the

interrupt pins, it is recommended that the functions and interrupt

mapping be done before enabling the interrupts. When changing

the configuration of an interrupt, it is recommended that the

interrupt be disabled first, by clearing the bit corresponding to that

function in the INT_ENABLE register, and then the function be

reconfigured before enabling the interrupt again. Configuration

of the functions while the interrupts are disabled helps to prevent

the accidental generation of an interrupt before desired.

The interrupt functions are latched and cleared by either reading the

data registers (Address 0x32 to Address 0x37) until the interrupt

condition is no longer valid for the data-related interrupts or by

reading the INT_SOURCE register (Address 0x30) for the

remaining interrupts. This section describes the interrupts that

can be set in the INT_ENABLE register and monitored in the

INT_SOURCE register.

DATA_READY

The DATA_READY bit is set when new data is available and is

cleared when no new data is available.

SINGLE_TAP

The SINGLE_TAP bit is set when a single acceleration event

that is greater than the value in the THRESH_TAP register

(Address 0x1D) occurs for less time than is specified in the

DUR register (Address 0x21).

Table 13. Interrupt Pin Digital Output

Parameter

Digital Output

Low Level Output Voltage (VOL)

High Level Output Voltage (VOH)

Low Level Output Current (IOL)

High Level Output Current (IOH)

Pin Capacitance

Rise/Fall Time

Rise Time (tR)2

Fall Time (tF)3

Test Conditions

IOL = 300 µA

IOH = −150 µA

VOL = VOL, max

VOH = VOH, min

fIN = 1 MHz, VIN = 2.5 V

CLOAD = 150 pF

CLOAD = 150 pF

DOUBLE_TAP

The DOUBLE_TAP bit is set when two acceleration events

that are greater than the value in the THRESH_TAP register

(Address 0x1D) occur for less time than is specified in the DUR

register (Address 0x21), with the second tap starting after the

time specified by the latent register (Address 0x22) but within

the time specified in the window register (Address 0x23). See

the Tap Detection section for more details.

Activity

The activity bit is set when acceleration greater than the value stored

in the THRESH_ACT register (Address 0x24) is experienced on

any participating axis, set by the ACT_INACT_CTL register

(Address 0x27).

Inactivity

The inactivity bit is set when acceleration of less than the

value stored in the THRESH_INACT register (Address 0x25) is

experienced for more time than is specified in the TIME_INACT

register (Address 0x26) on all participating axes, as set by the

ACT_INACT_CTL register (Address 0x27). The maximum value

for TIME_INACT is 255 sec.

FREE_FALL

The FREE_FALL bit is set when acceleration of less than the

value stored in the THRESH_FF register (Address 0x28) is

experienced for more time than is specified in the TIME_FF

register (Address 0x29) on all axes (logical AND). The FREE_FALL

interrupt differs from the inactivity interrupt as follows: all axes

always participate and are logically AND’ed, the timer period is

much smaller (1.28 sec maximum), and the mode of operation is

always dc-coupled.

Watermark

The watermark bit is set when the number of samples in FIFO

equals the value stored in the samples bits (Register FIFO_CTL,

Address 0x38). The watermark bit is cleared automatically when

FIFO is read, and the content returns to a value below the value

stored in the samples bits.

Min

0.8 × VDD I/O

300

Limit1

Max

0.2 × VDD I/O

−150

8

210

150

Unit

V

V

µA

µA

pF

ns

ns

1 Limits based on characterization results, not production tested.

2 Rise time is measured as the transition time from VOL, max to VOH, min of the interrupt pin.

3 Fall time is measured as the transition time from VOH, min to VOL, max of the interrupt pin.

Rev. E | Page 20 of 40

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