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VT1616

6-Channel AC97 Codec with S/PDIF

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VT1616 6-Channel AC97 Codec with S/PDIF

Power Management

The VT1616 may be placed in several power down states using the power down control bits located in index register

26h. Table 6 lists the power down states accessible through this register.

Table 6. Power Down Mode Bits

Bit

Function

PR0

ADC and Mux Powerdown

PR1

DAC Powerdown

PR2

Mixer Powerdown (VREF on)

PR3

Mixer Powerdown (VREF off)

PR4

AC Link Powerdown (BIT_CLK off)

PR5

Internal Clock Disabled

PR6

Alternate Line Out Powerdown

Note: Registers maintain values in sleep mode (PR4 write) and wake up with a warm reset (register values) or a cold reset (default values).

Power Down and Status register (index 26h) read action verifies stability before power down write action occurs.

PR0=1

PR1=1

PR2=1

PR4=1

Normal

ADC’s OFF

PR0

DAC’s OFF

PR1

Analog OFF

PR2 / PR3

Digital I/F

OFF

PR4

Shut Off

PR0=0

&

ADC=1

PR1=0

&

DAC=1

PR2=0

&

ANL=1

Warm Reset

Ready=1

Default

Cold Reset

Note: In this example, the Analog Mixer has been disabled, but VREF is still on.

Figure 5. AC’97 Power Down / Power Up Procedure

Complete power down of the AC’97 device is achieved by sequential writes to the Power Down and Status Control

Register (Index 26h) as follows:

Normal Operations:

ADC’s and Input Mux:

DAC’s:

Analog Mixer:

VREF_OUT:

AC-link:

Internal Clocks:

Alt. Line Out:

PR[6:0] = 00h

PR0 = 1 (write)

PR1 = 1 (write)

PR2 = 1 (write)

PR3 = 1 (write)

PR4 = 1 (write)

PR5 = 1 (write)

PR6 = 1 (write)

Revision 1.5, October 11, 2002

28

Data Sheet

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