PF28F1602C3TD70 Просмотр технического описания (PDF) - Intel

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PF28F1602C3TD70

Intel® Advanced+ Boot Block Flash Memory (C3)

Intel 

C3 SCSP Flash Memory

3.8.2

Programming the Protection Register (C0h)

The protection register bits are programmed using the two-cycle Protection Program command.

The 64-bit number is programmed 16 bits at a time for word-wide parts. First write the Protection

Program Setup command, C0h. The next write to the device will latch in address and data and

program the specified location. The allowable addresses are shown in Appendix E. See Figure 20

“Protection Register Programming Flowchart” on page 51.

Any attempt to address Protection Program commands outside the defined protection register

address space will result in a status register error (program error bit SR.4 will be set to 1).

Attempting to program or to a previously locked protection register segment will result in a status

register error (program error bit SR.4 and lock error bit SR.1 will be set to 1).

3.8.3

Figure 3.

Locking the Protection Register

The user-programmable segment of the protection register is lockable by programming Bit 1 of the

PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the

unique device number. This bit is set using the Protection Program command to program FFFDh to

the PR-LOCK location. After these bits have been programmed, no further changes can be made to

the values stored in the protection register. A Protection Program command to locked words will

result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1).

The protection register lockout state is not reversible.

Protection Register Memory Map

88H

4 Words

User Programmed

85H

84H

4 Words

Factory Programmed

81H

80H PR-LOCK

26 Aug 2005

24

Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family

Order Number: 252636, Revision: 004

Datasheet

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