ST16C1450IJ28 Просмотр технического описания (PDF) - Exar Corporation
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ST16C1450IJ28 Datasheet PDF : 32 Pages
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REV. 4.2.0
ST16C1450/51
2.97V TO 5.5V UART
TABLE 1: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
400
2400
4800
9600
19.2k
38.4k
76.8k
153.6k
230.4k
460.8k
921.6k
DIVISOR FOR 16x
Clock (Decimal)
2304
384
192
96
48
24
12
6
4
2
1
DIVISOR FOR 16x
Clock (HEX)
900
180
C0
60
30
18
0C
06
04
02
01
DLM PROGRAM
VALUE (HEX)
09
01
00
00
00
00
00
00
00
00
00
DLL PROGRAM
VALUE (HEX)
00
80
C0
60
30
18
0C
06
04
02
01
DATA RATE
ERROR (%)
0
0
0
0
0
0
0
0
0
0
0
2.4 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal clock.
A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits, inserts the
proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line
Status Register (LSR bit-5 and bit-6).
2.4.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.4.2 Transmitter Operation
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
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