ST16C1450IJ28(2005) Просмотр технического описания (PDF) - Exar Corporation
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ST16C1450IJ28 Datasheet PDF : 28 Pages
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REV. 4.2.1
ST16C1450
2.97V TO 5.5V UART
2.0 FUNCTIONAL DESCRIPTIONS
2.1 Internal Registers
The 1450 has a set of enhanced registers for controlling, monitoring and data loading and unloading. These
registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO
control register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers
(MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scractchpad
register (SPR). All the register functions are discussed in full detail later in “Section 3.0, UART INTERNAL
REGISTERS” on page 10.
2.2 Crystal Oscillator or External Clock
The 1450 includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to
the Baud Rate Generators (BRG) in the UART. XTAL1 is the input to the oscillator or external clock buffer input
with XTAL2 pin being the output. For programming details, see “Section 2.3, Programmable Baud Rate
Generator” on page 5.
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 3). Alternatively, an external
clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates.
Typical oscillator connections are shown in Figure 3. For further reading on oscillator circuit please see
application note DAN108 on EXAR’s web site.
FIGURE 3. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
C1
22-47pF
XTAL2
R2
500K - 1M
R1
0-120
(Optional)
Y1 1.8432 MHz
to
24 MHz
C2
22-47pF
2.3 Programmable Baud Rate Generator
The UART has its own Baud Rate Generator (BRG). The BRG divides the input crystal or external clock by a
programmable divisor between 1 and (216 -1) to obtain a 16X sampling clock of the serial data rate. The
sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor
(DLL and DLM registers) defaults to a random value upon power up or a reset. Therefore, the BRG must be
programmed during initialization to the operating data rate. Programming the Baud Rate Generator Registers
DLM and DLL provides the capability of selecting the operating data rate. Table 1 shows the standard data
rates available with a 14.7456 MHz crystal or external clock at 16X clock rate. When using a non-standard data
rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency) / (serial data rate x 16)
5
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