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C513AO-2E Просмотр технического описания (PDF) - Infineon Technologies

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C513AO-2E
Infineon
Infineon Technologies Infineon
C513AO-2E Datasheet PDF : 59 Pages
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C513AO
Table 1
Pin Definitions and Functions (cont’d)
Symbol Pin Number
P- DIP P-LCC- P-MQFP-
-40 44
44
I/O Function
*)
P3.0-
P.3.7
10-17 11,
5,
13-19 7-13
I/O Port 3
Port 3 is an 8-bit quasi-bidirectional port with internal
pull-up arrangement. Port 3 pins that have “1”s
written to them are pulled high by the internal pull-up
transistors and in that state can be used as inputs.
As inputs, Port 3 pins being externally pulled low will
source current (IIL, in the DC characteristics)
because of the internal pull-up transistors.
The output latch corresponding to a secondary
function must be programmed to a “1” for that
function to operate (except for TxD and WR).
The secondary functions are assigned to the pins of
Port 3 as follows:
10
11
5
11
13
7
12
14
8
13
15
9
14
16
10
15
17
11
16
18
12
17
19
13
RESET 9
10
4
*) I = Input
O = Output
P3.0 / RxD
P3.1 / TxD
P3.2 / INT0
P3.3 / INT1
P3.4 / T0
P3.5 / T1
P3.6 / WR
P3.7 / RD
Receiver data input (asynch.)
or data input/output (synch.) of
serial interface
Transmitter data output
(asynch.) or clock output
(synch.) of serial interface
External Interrupt 0 input /
Timer 0 gate control input
External Interrupt 1 input /
Timer 1 gate control input
Timer 0 counter input
Timer 1 counter input
WR control output; latches the
data byte from Port 0 into the
external data memory
RD control output; enables the
external data memory to Port 0
I RESET
A high level on this pin for the duration of two
machine cycles while the oscillator is running resets
the device. An internal diffused resistor to VSS
permits power-on reset using only an external
capacitor to VDD.
Data Sheet
8
02.00

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