21.2-S3-C2410X-052003 Просмотр технического описания (PDF) - Samsung

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21.2-S3-C2410X-052003

32-Bit RISC Microprocessor

Samsung 

Table of Contents (Continued)

Chapter 21 IIS-Bus Interface

Overview ................................................................................................................................................ 21-1

Block Diagram ........................................................................................................................................ 21-2

Functional Descriptions........................................................................................................................... 21-2

Transmit or Receive only Mode ...................................................................................................... 21-2

Audio Serial Interface Format ................................................................................................................. 21-3

IIS-Bus Format ............................................................................................................................... 21-3

MSB (Left) Justified ........................................................................................................................ 21-3

Sampling Frequency and Master Clock........................................................................................... 21-4

IIS-Bus Interface Special Registers......................................................................................................... 21-5

IIS Control (IISCON) Register......................................................................................................... 21-5

IIS Mode Register (IISMOD) Register ............................................................................................. 21-6

IIS Prescaler (IISPSR) Register ...................................................................................................... 21-7

IIS FIFO Control (IISFCON) Register.............................................................................................. 21-8

IIS FIFO (IISFIFO) Register............................................................................................................ 21-8

Chapter 22 SPI Interface

Overview ................................................................................................................................................ 22-1

Features ......................................................................................................................................... 22-1

Block Diagram................................................................................................................................ 22-2

SPI Operation................................................................................................................................. 22-3

SPI Special Registers ............................................................................................................................. 22-7

SPI Control Register....................................................................................................................... 22-7

SPI Status Register ........................................................................................................................ 22-8

SPI Pin Control Register................................................................................................................. 22-9

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S3C2410X MICROPROCESSOR

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